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This paper seeks to address the disconnect between different stages of the FPGA CAD flow that often adversely affects the quality of results of the implemented designs. In particular, a machine-learning framework is presented, consisting of a suite of classification and regression techniques, to model the underlying relationship between the characteristics of circuits and the best CAD algorithm (and...
Bitstream-based simulation approach was proposed and experimentally validated by heavy ions and protons in Xilinx Virtex-4 FPGAs. The simulation approach is able to predict the probability of an SEU to reduce a functional failure. With the existence of the SEU sensitivity data of the configuration memories, the functional failure probability of any implemented circuit can be calculated not by experiment...
FPGA architecture exploration is a topic of great interest to hardware researchers. By synthesizing many hardware descriptions with different architecture specifications, it is possible to compare the generated circuits and draw a conclusion about those specifications. In order to be confident in results obtained from this exploration, it is necessary to verify that the circuits have been compiled...
Field Programmable Gate Arrays (FPGAs) are susceptible to many environment effects that can cause soft errors (errors which can be corrected by the reconfiguration ability of the FPGA). Two different fault models are discussed and compared in this paper. The first one -- Stuck-at model -- is widely used in many applications and it is not limited to the FPGAs. The second one -- Bit-flip model -- can...
This paper investigates the use of reconfigurable computing and readily available Field Programmable Gate Array (FPGA) platforms to expedite the generation of input-patterns for testing integrated circuits after manufacture. In this paper, we describe our techniques that efficiently identify the fault locations and the most effective input patterns by leveraging the parallel nature of the FPGA hardware...
Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) due to NBTI is further affected by the initial value of Vth from fabrication-induced process variation (PV). Addressing these challenges in embedded FPGA designs is possible, as FPGA reconfigurablility can be exploited to measure the...
Spatially-tiled architectures, such as coarse-grained reconfigurable arrays (CGRAs), are powerful architectures for accelerating applications in the digital-signal processing, embedded, and scientific computing domains. In contrast to field-programmable gate arrays (FPGAs), another common accelerator, they typically time-multiplex their processing elements and are word rather than bit-oriented. These...
With rapid advances in integrated circuit technology, wirelength has become one of the most critical and important metrics in all phases of VLSI physical design automation, especially circuit placement. As the precise wirelength for a given placement can only be known after routing, accurate and fast-to-compute wirelength estimates are required by FPGA placement algorithms. In this paper, a new model,...
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