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Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable...
In this study, a novel power efficient implicit pulsed-triggered flip-flop with embedded clock-gating and pull-up control scheme (IPFF-CGPC) is proposed. By applying an XOR-based clock-gating scheme in the pulse generating stage, which conditionally disables the inverter chain when the input keeps unchanged, IPFF-CGPC is able to gain low power efficiency by eliminating redundant transitions of internal...
In this paper, we introduce a systematic power analysis framework for SoC designs using bottom-up power modeling integrated with top-down power estimation. Four power analysis tools have been realized: (1) PowerBrick, a power characterization tool to construct power libraries for standard cell library and memory compiler, (2) PowerMixer, an RTL/gate-level power estimator for large logic design, (3)...
Flip-flops (FF) typically consume more than 50% of random-logic power in an SoC chip, due to their redundant transition of internal nodes, when the input and the output are in the same state. Several low-power techniques have been proposed, but all of them incur transistor-count penalties, leading to an increase in size, which is too costly since flip-flops typically account for 50% of random-logic...
Designing aliasing-free space support hardware for built-in self-testing in very large scale integration circuits and systems is of immense significance, specifically due to the design paradigm shift in recent years from system-on-board to system-on-chip. This paper develops an approach to designing aliasing-free space compaction hardware targeting particularly embedded cores-based system-on-chips...
Engineering change orders (ECOs), which are used to apply late-stage specification changes and bug fixes, have become an important part of the field-programmable gate array design flow. ECOs are beneficial since they are applied directly to a placed-and-routed netlist which preserves most of the engineering effort invested previously. Unfortunately, designers often apply ECOs in a manual fashion which...
The high speed dual phase operation domino circuit, which includes high-performance and reliable characteristics is proposed, and the circuit design technique with practical implementation is presented. The cell-based automatic synthesis flow supports the quick design of high performance chips. The test chip of a dual-phase 64 bit high-speed multiplier with a built-in performance adjustment mechanism...
Structured ASIC, which consists of a homogeneous array of tiles, suffers from large delay and area due to its inherent regularity. A new lithography method called selectively patterned masks (SPM) is proposed. It exploits special masks called masking masks and double exposure technique to allow more than one types of tiles to be patterned on the same wafer. The result is a heterogeneous array of tiles,...
Low power design has become one of the most significant requirements when CMOS technology entered the nanometer era. Therefore, timing budget is often performed to slow down as many components as possible so that timing slacks can be applied to reduce the power consumption while maintaining the performance of the whole design. Retiming is a procedure that involves the relocation of flip-flops (FFs)...
This paper proposes utilisation of polymorphic electronics to design digital circuit controllers that gracefully degrades when some inconvenient situation arise, e.g. when battery goes low or a chip temperature cross some safe level. In proposed approach, the next state logic of the controller is designed using polymorphic gates. Polymorphic gates exhibit two or more logic functions in according to...
This paper presents a new dynamic circuit design style based on the differential cascade voltage swing logic. The design style is proposed as a data driven dynamic differential logic design style. The proposed design style offers significant performance advantages over conventional DCVSL and Differential Domino with reduced power consumption. The pre-charge and evaluation phases are controlled by...
Energy efficiency and idle power consumption are becoming important parameters in the design of embedded systems that are realized with nanometer-scale CMOS devices. In nanometer-scale CMOS, Excessive quiescent power dissipation can lead to excessive heat generation and reliability issues. To address energy efficiency and idle power consumption, we present a novel Complementary Nano-Electro-Mechanical...
In this paper we present a new software framework to analyze and modify circuits netlists in an automatic fashion. We developed an API that implements low-level functionalities above which it is possible to create complex algorithms. We then developed a second software layer to implement hardening techniques for Single Event Effects (SEEs) in digital microcircuits. Experimental results prove the effectiveness...
Charge recovery is a promising concept to design (cryptographic) VLSI circuits with low energy dissipation. However, unsatisfactory designs of proposed logic cells degrade its theoretical efficiency significantly both in its energy consumption and the resistance against differential power analysis attacks (DPA-attacks). Short circuit dissipation and non-adiabatic discharging of capacitance loads are...
A desirable characteristic of VLSI circuits is high speed operation. The use of dynamic circuit design techniques can provide high speed operation at lower silicon area requirements, compared to full static CMOS designs. Another common design technique in order to achieve high operating speed is the use of pipeline schemes. However, the higher the required operating frequency, the higher the number...
With the device scaling up to nano-level, the integrated circuits are expected to face high computing error rates. This increased rate is the outcome of random and dynamic noise injected in the circuit which becomes more vulnerable due to low supply voltages and extremely small transistor dimensions. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit...
Nowadays, the integrated circuits design and manufacturing process are decreasing the minimum transistor size and this advancement, accompanied by increasing operating frequencies and lower power supplies voltages, leads, on the one side, to the availability of fast and low power circuits with very small noise margins but, on the other side, makes integrated circuits more sensitive to Single Event...
A compact model of III-V HFETs is developed for digital logic circuit applications such as a 6T-SRAM cell. We study sub-22 nm technology III-V SRAM circuit design via III-V MOSFETs with thin high-k dielectric for low gate tunneling current, and optimized extrinsic structure for minimum parasitic capacitance. We investigate the drawbacks of a weak PMOS device in a SRAM cell and propose a minimum requirement...
Since the introduction of energy harvesting and battery powered low- to mid-speed electronic circuits, supply voltages have been pushed to the physical limits of semiconductor devices for energy minimization and battery lifetime. Using the IBM 8RF-LM 0.13 ??m process and a modified library, an asynchronous ALU has shown to be capable of operating at 0.1 V. This paper presents the minimum energy analysis...
The Wave Dynamic Differential Logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against Differential Power Attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-rail signals in WDDL design....
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