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Proliferation of handheld devices and growing interests in pervasive computing has led to the need for more flexible communication solutions where a single device integrates various wired and wireless communication standards e.g. Asymmetric Digital Subscriber loop (ADSL), Very high speed Digital Subscriber Loop (VDSL), Digital Audio Broadcasting (DAB), Digital Video Broadcasting (DVB-T/H) and 802...
Fast and efficient accumulation arithmetic circuits are critical for a broad range of scientific and embedded system applications. High throughput accumulation circuits are typically hand designed for specific vector lengths requiring the circuit to be modified when the lengths are changed. In this work we present a new design approach that can achieve low latency and near optimal throughput for input...
This paper presents the design and analysis of an area efficient implementation of the SHA-3 candidate Blue Midnight Wish (BMW-256) hash function with digest size of 256 bits on an FPGA platform. Our architecture is based on a 32 bit data-path. The core functionality with finalization implementation without padding stage of BMW on Xilinx Virtex-5 FPGA requires 84 slices and two blocks of memory: one...
The newest generation of sequencing instruments, such as Illumina/Solexa Genome Analyzer and ABI SOLiD, can generate hundreds of millions of short DNA “reads” from a single run. These reads must be matched against a reference genome to identify their original location. Due to sequencing errors or variations in the sequenced genome, the matching procedure must allow a variable but limited number of...
This paper proposes a programmable 2-D DWT system architecture designed for the JPEG-2000 standard. The proposed system architecture, derived from an iterative design space exploration process using Altera's C2H compiler, provides a significant performance acceleration of 2-D DWT when compared to an optimized 2-D DWT software implementation and is capable of real-time video processing performance...
The configurable routing in asynchronous FPGAs accounts for 80-90% of the total area and consumes 80-90% of the total power. This paper presents an asynchronous FPGA that applies two techniques to reduce power consumption. First, the routing is altered to use two-phase logic rather than four-phase logic. Second, enable (acknowledge) signals are voltage scaled such that the overall FPGA performance...
Dynamic and partial reconfiguration of Xilinx FPGAs is a well known technique in runtime adaptive system design. With this technique, parts of a configuration can be substituted while other parts stay operative without any disturbance. The advantage is the fact, that the spatial and temporal partitioning can be exploited with the goal to increase performance and to reduce power consumption due to...
Network on chip (NoC) has been proposed as new on-chip communication paradigm for the multi-core processing era. But the memory wall problem is a design bottleneck, especially in real-time applications. This paper proposes a high throughput memory data-path design that can guarantee real-time I/O throughput for an in-house developed multi-core system. The main contribution is as follows: Firstly,...
This paper presents a field-programmable gate array (FPGA) implementation of an unbiased minimum mean square error (MMSE) metric based QR-decomposition M (QRDM) algorithm for the multiple-input multiple-output (MIMO) systems. Two advanced techniques, namely the merge-sort (MS) based and winner path expansion (WPE) based sorting schemes have been implemented and validated on an FPGA platform for a...
Complex reciprocal and square-root operations are used in many digital signal processing (DSP) and numerical computations. In particular, high-throughput fixed-point implementations are desired in high-performance systems. This brief describes a novel design of high-throughput 16-bit fixed-point complex reciprocal/square-root unit. Our approach uses an interpolation algorithm based on the 2-D cubic...
This paper examines the feasibility of utilizing a grid of asynchronously clocked run-time reconfigurable modules (RTRMs) on a dynamically and partially reconfigurable (DPR) FPGA. In contrast to a synchronously clocked grid studied in research, the design, the implementation, the performance and the resource utilization of an asynchronously clocked grid is shown. Such a run-time reconfigurable (RTR)...
Capacity of FPGAs has grown significantly, leading to increased complexity of designs targeting these chips. Traditional FPGA design methodology using HDLs is no longer sufficient and new methodologies are being sought. An attractive possibility is to use streaming languages. Streaming languages group data into streams, which are processed by computational nodes called kernels. They are suitable for...
This paper presents an FPGA implementation of a low cost 8 bit reconfigurable processor core for media processing applications. The core is optimized to provide all basic arithmetic and logic functions required by the media processing and other domains, as well as to make it easily integrable into a 2D array. This paper presents an investigation of the feasibility of the core as a potential soft processing...
Since its adoption as a new encryption standard by NIST, the Advanced Encryption Standard (AES) has become the default choice for various applications. On the other hand, a straightforward implementation of the AES is vulnerable to different forms of side channel attacks. In this paper, we explore several countermeasure techniques against power analysis attacks. In particular, we present an area optimized...
In this paper, we present a FPGA prototyping of the MIMO Decoder for the IEEE 802.16e WiMAX mobile systems. The IEEE 802.16e standard supports three types of MIMO space time codes (STC), referred to in the standard by matrix A, B, and C, that achieve different levels of throughput and diversity depending on the quality of the MIMO channels. In particular, the STC matrix A achieves full diversity by...
Emulation of a large system on a multi-FPGA platform not only involves partitioning the system into multiple modules subject to given capacity and resource constraints, but also involves achieving higher throughput, lower cost of emulation and less communication overhead. Many good scheduling algorithms have been reported, however due to the lack of pipelining they fail to achieve high system throughput...
This paper studies on the hardware design and implementation of a universal multi-DSP and FPGA image information processor in accordance with the PCI-E and CPCI specifications. The image information processor features two clusters of total four ADSP-TS201 TigerSHARC DSPs from ADI as the kernel processing unit, reconfigurable framework implemented by two Xilinx Virtex-5 FXT FPGA chips. Taking full...
Recent breakthroughs in cryptanalysis of standard hash functions like SHA-1 and MD5 raise the need for alternatives. The MD6 hash function is developed by a team led by Professor Ronald L. Rivest in response to the call for proposals for a SHA-3 cryptographic hash algorithm by the National Institute of Standards and Technology. The hardware performance evaluation of hash chip design mainly includes...
Matrix decomposition is required in various algorithms used in wireless communication applications. FPGAs strike a balance between ASICs and DSPs, as they have the programmability of software with performance capacity approaching that of a custom hardware implementation. However, FPGA architectures require designers to make a countless number of system, architectural and logic design decisions. By...
In this paper, we propose a high-speed parallel GF(2128) bit multiplier for Ghash function in conjunction with its FPGA implementation. Through the use of Verilog the designs are evaluated by using Xilinx Vertax5 with 65 nm technic and 30,000 logic cells. The highest throughput of 30.764 Gpbs can be achieved on Virtex5 with the consumption of 8864 slices LUT. The proposed design of the multiplier...
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