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The high processing complexity of data detection in the large-scale multiple-input multiple-output (MIMO) uplink necessitates high-throughput VLSI implementations. In this paper, we propose — to the best of our knowledge — first matrix inversion implementation suitable for data detection in systems having hundreds of antennas at the base station (BS). The underlying idea is to carry out an approximate...
This paper presents a Radix-2 Single-Path Delay Feedback (R2SDF) configurable processor to calculate 64/128/512/1024/2048-point Fast Fourier Transform (FFT). Such range of FFT input sequences allows for the realization of the widely used wireless protocols IEEE 802.11n (WLAN) and the IEEE 802.16 (WiMax). The presented R2SDF configurable processor, as well as a fully sequential configurable processor...
This paper reports a new speed record for FPGAs in cracking Elliptic Curve Cryptosystems. We conduct a detailed analysis of different F2(m) multiplication approaches in this application. A novel architecture using optimized normal basis multipliers is proposed to solve the Certicom challenge ECC2K-130. We compare the FPGA performance against CPUs, GPUs, and the Sony PlayStation 3. Our implementations...
This paper presents a novel high-speed, low-complexity 128/64-point radix-24 FFT/IFFT processor for the applications in a high-throughput MIMO-OFDM systems. The high radix radix-24 multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT...
Dynamic reconfiguration capabilities of FPGA devices are commonly exploited in order to perform changes in a system with respect to computational elements. In this paper, we propose a framework able to exploit different levels of simulations in order to perform a requirements-driven design of the communication infrastructure of a reconfigurable system, so that the overall performances can be improved...
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