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A droplet-born air-blowing method is an advanced method of the drawing lithography enables simple and fast fabrication, which does not require UV irradiation or moulding process. However, it has disadvantages such as low throughput in the formation of droplet array as it uses the dispenser to make droplets one by one. To increase the throughput while also simplifying the fabrication method, we suggest...
This paper presents a new method for making three-dimensional structure on the surface of an elastomer substrate. In general, micromachining based on lithography process is layer-by-layer fabrication, and the resulting structure is restricted to be two-dimensional. In this paper, we presented that three-dimensional structures were achieved by attaching a thin film partially onto an elastomer. Under...
Organic-inorganic hybrid perovskite solar cells have emerged as a leading renewable energy technology in photovoltaic. Despite many advantageous in perovskite solar cells, the perovskite absorbing layer quality was not uniform such crystallinity, surface coverage. Here we report a novel fabrication method using UV O2 plasma process by controlling the surface reactivity for high crystallinity perovskite...
A recent trend in biosensors and biomedical devices is the fabrication of compact, high aspect ratio and free-standing biocompatible structures with application as force sensors, microneedle-based drug delivery systems, array of chemical sensors, etc. SU-8 photoresist is a promising candidate to fulfill such structure. Poly(Dimethylsiloxane) has been used as the sacrificial layer to successfully release...
This paper reports a three-step fabrication method for highly ordered silica nanowire bunch arrays of diversiform shapes. After patterning of organic polymers on Si substrates through photo lithography, oxygen plasma bombardment is applied to fabricate nanowire bunch arrays. On one hand, oxygen plasma exploits Si source from the substrates, and, subsequently, the gaseous Si react with active oxygen...
We report in CPEM 2012 the preparation of the micromechanical cleavage (MC) and the chemical vapor deposition (CVD) graphene films and the fabrication of the quantum Hall resistance (QHR) devices on these films. Graphene films are on the SiO2/Si substrates. Spectroscopic Raman analysis indicates monolayer graphene films are obtained. Hall bar structures are formed on graphene films by e-beam lithography,...
This paper presents a PDMS micro through-hole molding method by simple soft lithography process in which the surface of a master mold and a substrate is treated by atmospheric CH4/He RF plasma to feature hydrophobic property on the surface. Rectangular and circular-shaped PDMS micro through-hole layers are made by the proposed fabrication method. As one of the applications of the PDMS micro through-hole...
A low-temperature hydrogenation-assisted sequential deposition and crystallization technique is reported for the preparation of nano-scale silicon quantum dots suitable for light-emitting applications. The preparation of layers of quantum dots was by RF plasma-enhanced deposition and in-situ treatment of an amorphous silicon film followed by reactive-ion etching to create the nanoscale features. The...
We present for the first time an approach to fabricate surface enhanced Raman scattering (SERS)-active substrates based on nanofibers simply by removing SU-8 photoresist in oxygen plasma bombardment. Compared with Raman spectral signals of Rhodamine B on smooth silicon substrates, the intensity of those on the nanofiber-based SERS-active substrates are much more distinctive and are at least 103 folds...
Summary form only given. Plasma polymerization, so called remote plasma enhanced chemical vapour deposition (RPECVD) has been increasingly used in microsystems field. Plasma polymers served primarily as supports for electronic sensors or carriers for biomolecules and cell attachment. This work describes the first use of plasma thin film deposition for the easy, fast and reduced cost fabrication of...
Assembly of colloidal arrays has attracted much attention over the past decade. Surface property and topology play important roles in the assembly of colloidal patterns and layers on various substrates. In this paper, we report on a novel micropattern-assisted nanoassembly (muPAN) method to organize highly ordered nanocolloidal arrays onto a nonfouling polymer surface. Polyethylene glycol (PEG) hydrogel...
An independent-gate four-terminal FinFET SRAM have been successfully fabricated for drastic leakage current reduction. The new SRAM is consisted of a four-terminal (4T-) FinFET which has a flexible Vth controllability. The 4T-FinFET with a TiN metal gate is fabricated by a newly developed gate separation etching process. By appropriately controlling the Vth of the 4T-FinFET, we have successfully demonstrated...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
The notching phenomenon has been observed during high aspect ratio silicon etching while performing an etch stop on a dielectric layer. It is generally considered as a critical issue in the fabrication of MEMS structures on SOI substrates. This article reports a novel solution for the elimination of the notching while using conventional non-pulsed RF substrate biasing.
A new type of precision thinned bonded silicon wafer is evaluated for thin film CMOS/SOI applications. SOI wafers with silicon film thickness variations of less than ??2.5 nm are available with choice of substrate doping and buried oxide thickness. CMOS devices fabricated on these wafers have the same carrier mobilities as comparable bulk silicon MOSFETs.
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