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Using active feedback technique an analogue four quadrant multiplier-divider presented in this paper has achieved a great dynamic range both at inputs and at the output, and a good linearity with nonlinearity error smaller than 2%. Moreever the circuit has a better independence from the manufacturing process and the geometrical size of MOS transistors.
A comparator-based circuit that uses switched-capacitor charging replaces the op amp in the multiplying digital-to-analog converter (MDAC) of a low-voltage algorithmic ADC. MDAC output swing beyond Vdd allows greater than rail-to-rail ADC input range. At a supply voltage of 0.55 V, the ADC achieves 8.4 bit ENOB and 1.4 Vpp differential input range. It occupies 0.65 mm2 in 0.25-μm CMOS and dissipates...
In recent years, we have seen the emergence of multi-GS/s medium-to-high-resolution ADCs. Presently, SAR ADCs dominate low-speed applications and time-interleaved SARs are becoming increasingly popular for high-speed ADCs [1,2]. However the SAR architecture faces two key problems in simultaneously achieving multi-GS/s sample rates and high resolution: (1) the fundamental trade-off of comparator noise...
This project presents the implementation of error reduction techniques in sample and hold circuit(S/H).S/H suffers from multiple errors such as droop, acquisition error, aperture jitter, etc. Mainly two hold mode errors that is charge injection and clock feedthrough. We are trying to mitigate these errors by using different design techniques. When a switch in the S/H turns on, the capacitor starts...
This paper presents an ultra-low-power low-voltage Class-AB Fully Differential Operational Amplifier designed in 45-nm CMOS technology. The proposed circuit uses transistors operating in sub-threshold region for low-power and low-voltage operation. The proposed Op Amp offers an open-loop gain of 74.6 dB, 1 MHz unity gain frequency, 50-degrees Phase Margin, and 91.55 dB common-mode rejection ratio...
This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive...
This paper proposes a design of an Operational Amplifier which uses an Adaptive biasing circuitry along with an auxiliary circuit to improve the Slew Rate. One auxiliary circuit have been added to the differential amplifier in order to improve its Slew Rate. The Power Dissipation of the circuit is well controlled by the auxiliary circuit as auxiliary circuit comes into play only during large transients...
A simple design methodology of the capacitive front-end readout electronics, based on the negative impedance converter, is presented. The concept uses a parallel connection of positive and inverted-negative value capacitors, that allows removing the constant part C0 from the sensor gain transfer function. The circuit enables integration of an accurate and very sensitive capacitance-to-voltage converter...
In this paper, a low voltage fully differential neural amplifier based on current feedback operational amplifier (CFOA) is introduced. The gains of LFP and spikes signals can be tuned using the amplifiers capacitors. The designed amplifier provides a maximum output gain up to 50 dB, a total power consumption of 4.218 nW, and an input referred noise of 3.38 μV/Hz1/2 and 5.96 μV/Hz1/2 for LFP signals...
A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement...
An auto-zero operational amplifier dedicated to space applications is proposed. Its operation principle is based on a continuous-time auto-zeroed amplifier topology to provide a low-level offset. The circuit was implemented in a standard 130 nm CMOS technology. Simulations show that the residual offset is reduced to a few microvolts. The gain bandwidth product is estimated at 10 MHz, and the slew-rate...
In this work a low power 5th order chebyshev active-RC low pass filter that meets Rel-8 LTE receiver requirements has been designed with programmable bandwidth and overshoot. Designed for a homodyne LTE receiver, filter bandwidths from 700kHz to 10MHz are supported. The bandwidth of the operational amplifiers is improved using a novel phase enhancement technique. The filter was implemented in 65nm...
This paper presents an 8-bit folding analog-digital converter (ADC) using switched capacitors. In this architecture, the conversion is achieved when the signal crosses a determined voltage level and at this time, a voltage value is added or subtracted from the analog input signal. The ADC proposed consists of eight identical stages that perform the conversion of one bit at a time. Each stage consists...
A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme...
We report an 11-b 20-Ms/s pipelined ADC in 0.18-μm CMOS with a novel dual-mode-based digital background calibration method that altogether corrects errors caused by gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables an intentional use of low-gain single-stage op amps instead of conventional high-gain multi-stage op amps, with which we achieve a total ADC power...
In this paper a novel compensation method for low power two-stage operational Amplifiers is proposed. The proposed model is used 50 nm CMOS technology and employs a 50 femto Farad capacitor as the compensation capacitor. Although the method uses Miller effect compensation as the compensation method, the compensation capacitor plays its rule in an indirect way. The proposed method has simulated and...
We demonstrated the feasibility of the adaptive frequency compensation approach to design maximum- and constant-bandwidth feedback amplifiers. A basic CMOS amplifier exhibiting 66-dB dc gain and 310-MHz gain-bandwidth product was designed. For closed-loop gains ranging from 1 to 10, the closed loop bandwidth was found never lower than 401 MHz. A similar amplifier with equal gain-bandwidth product,...
Multistage operational amplifiers suitable for nanometer-scale CMOS technologies and low-voltage applications are described. The low intrinsic gain of transistors is compensated for with cascade of single-stage amplifiers. Techniques for compensations are revisited and the optimal solution identified. An example of a novel scheme that achieves 67 dB of DC gain, 320 MHz of bandwidth and 61 degrees...
This paper presents a high-speed CMOS OP Amp with a dynamic switching bias circuit capable of processing video signals of over 2 MHz with slight nonlinearity and low dissipated power. The OP Amp, capable of operating at 10 MHz dynamic switching rate, was designed and showed through simulations a dissipated power of 60 % of that in conventional continuous operation. A switched capacitor (SC) non-inverting...
In this paper, an interface circuit for integrated capacitive sensors is designed and simulated by Spectre of Cadence software with TSMC 0.18μm complementary metal oxide semiconductor (CMOS) process. This circuit converts the capacitance of sensing capacitor to the voltage change based on switched-capacitor circuit. The results show the sensitivity of 1mV/10fF and the circuit removes the effect of...
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