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A number of critical design decisions, such as network topology, buffer sizes, flow control mechanism and so on so forth, have to be evaluated in any NoC the design. Designs and verifications of NoCs are based on either software simulations, which are extremely slow and inaccurate for complex models, or hardware emulations using low/mid-class FPGAs, where the scalability of the NoC system is intensively...
This paper introduces cycle-reconfigurable modules that enhance FPGA architectures with efficient support for dynamic data accesses: data accesses with accessed data size and location known only at runtime. The proposed module adopts new reconfiguration strategies based on dynamic FIFOs, dynamic caches, and dynamic shared memories to significantly reduce configuration generation and routing complexity...
Error detection and locating during the post-silicon stage is a critical concern in modern IC industry. Especially timing errors caused by uncertain variations and electrical bugs are by far lacking effective methods to debug. In order to meet this challenge, we propose an on-line timing error detection method, which uses the on-chip storage to hold the golden execution trace by running the test program...
This paper is on FPGA based emulation which is one the approaches to perform pre-silicon SoC validation, accelerate system software development and to meet time-to-market demands. This paper presents a verification methodology of SoC and also deals with simplified implementation of complex clock designs in FPGA are presented, which needs to be skillfully handled to meet the said criteria. Each base...
Partial reconfiguration (PR) enhances traditional FPGA-based system-on-chips (SoCs) by providing additional benefits such as reduced area and increased functionality as compared to non-PR SoCs. However, since leveraging these additional benefits requires specific designer expertise and increased development time, PR has not yet gained widespread usage. In this paper, we present an integrated development...
In modern SoC design flow, verification and validation are key components to reduce time-to-market and enhance product quality. To avoid trade-offs between timing accuracy and simulation speed in RTL simulation and C++/SystemC virtual prototyping, FPGA prototyping has become a better choice in the design flow. However, the time-consuming bring-up procedure and insufficient debugging visibility has...
The use of synthesizable reconfigurable IP cores has increasingly become a trend in System on Chip (SoC) designs because of their flexibility and powerful functionality. The market introduction of multi-featured platform FPGAs equipped with embedded memory and processor blocks has further expanded the possibility of utilizing dynamic reconfiguration to improve overall system adaptability to meet varying...
Due to the continuously decreasing cost of FPGAs, they have become a valid implementation platform for SOCs. Typically, a soft core processor implementation is used to execute the software parts of the SOC. As each system is individually designed for a particular application, the idea is natural to support compute intensive parts of the code through customized hardware acceleration. Two different...
This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance...
The new generation of field programmable gate array(FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip(SOPC) developing environment. Therefore, this study presents a speed control integrated circuit(IC) for stepping motor drive under this SOPC environment. The design, using FPGA of Spartan-3E series,...
A flexible hardware accelerator for full-search vector quantization (VQ) has been developed as a component for a system on a programmable chip (SoPC) to use in real- time image compression and recognition applications. In the system, the number of elements for each codeword and the number of codewords in the system can be changed easily for different applications with the use of an embedded CPU. The...
Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only profitable if the costs in terms of area, energy and delay for reliability keep within limits. Therefore, the traditional worst case design methodology will become infeasible. Future architectures have to be error resilient,...
This paper addresses problems associated with verification and FPGA prototyping platform preparation for the pre-silicon software development. Increasing the size of modern SoC makes traditional approach of mapping entire design into one FPGA unsuitable. Consequently, other more appropriate scheme must be found in order to achieve optimal results. One solution for the problem could be platforms with...
The advantages and the flexibility introduced into the hardware implementation by partial dynamic reconfiguration have rapidly changed the design flow of embedded systems. Configuration management is an important issue in operating system for dynamically reconfigurable system-on-chip. Reconfiguration overhead affects the performance of reconfigurable system. This paper presents a hardware implemented...
Field programmable gate arrays (FPGAs) are commonly used as an inexpensive and flexible implementation platform for system-on-chip (SoC) designs. Now that FPGAs are large enough to implement SoCs, the reprogrammable fabric allows a different approach to the design process where on-chip computer aided design (CAD) tools can leverage reconfigurability to reduce design time. Statistics on commercial...
in this paper, we introduce an auto-adaptation method for reconfigurable system-on-chip (SoCs) architectures. The approach is based on joint dynamic frequency scaling and the partial and dynamic reconfiguration technique. The method aims the enhancement of the global auto-adaptability of SoCs in terms of energy, efficiency and scalability. The auto-adaptation method is described and tested with the...
FPGA based multiprocessor SoC (MPSoC) is an on-chip multiprocessor with fully programmable feature which can reduce development cost and achieve performance requirement. In order to provide an MPSoC with the low-overhead communication and synchronization methods, this paper attempts to introduce the TSVM (tagged shared variable memory) cache to a snooping cache on the MPSoC. The TSVM cache can improve...
Perceiving a color difference is different from identifying the colors causing the difference. The former is a subtask of the latter that involves the tasks of color identification and color difference perception. In this paper, a technique capable of detecting specific color edges in an image is proposed. Instead of developing an efficient algorithm for detecting edges caused by specific colors,...
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