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Such advantages as self-adaption, multi-functions, low cost and low power etc make the technology of reconfiguration be the development tread of embedded system. The aim of this paper is to give a reconfigurable, embedded and fault-tolerent electronic control system architecture oriented to space application using the technology of reconfiguration. In order to support this architecture, the reconfigural...
Reconfigurable Field Programmable Gate Arrays (FPGAs) are growing the attention of developers of mission- and safety-critical applications (e.g., aerospace ones), as they allow unprecedented levels of performance, which are making these devices particularly attractive as ASICs replacement, and as they offer the unique feature of in-the-field reconfiguration. However, the sensitivity of reconfigurable...
Power and fault tolerance are deemed to be two orthogonal optimization objectives in FPGA synthesis, with independent attempts to develop algorithms and CAD tools to optimize each objective. In this paper, we study the relationship between these two optimizations and show empirically that there are strong ties between them. Specifically, we analyze the power and reliability optimization problems in...
An Autonomous Fault-Tolerant System (AFTS) refers to a system that is able to configure its own resources in the presence of permanent defects and spontaneous random faults occurring in its silicon substrate in order to maintain its functionality. This work analyzes how AFTS could be built, specifically focusing on hardware platform dependant issues, and gives an overview of the state-of-the-art in...
A method and architecture for synchronization of Fault-Tolerant system implemented in FPGAs is proposed. It is based on repairing faulty units and transferring of the fault-free state of the system to the unit under repair. Its architecture is based on the previously designed model which is extended for usage in more complex systems. The proposed method was implemented on an FPGA and the experimental...
One trend dealing with the growing computational power needs is to implement multi-processor system-on-a-chip (MPSoC) using Commercial Off-The-Shelf (COTS) partially reconfigurable architectures. However the low Non-Recurring Engineering (NRE) cost solution provided by commercial FPGAs must take into account the high sensitivity to electronic defects. Fault-tolerance schemes, which prevent their architectures...
This paper presents a novel approach to exploit FPGA dynamic partial reconfiguration to improve the fault tolerance of complex microprocessor-based systems, with no need to statically reserve area to host redundant components. The proposed method not only improves the survivability of the system by allowing the online replacement of defective key parts of the processor, but also provides performance...
Activities which aim at developing a methodology of fault tolerant systems design into FPGA platforms are presented. Basic principles of partial reconfiguration are described together with the fault tolerant architectures based on the partial dynamic reconfiguration and triple modular redundancy or duplex system. Several architectures using online checkers for error detection which initiates reconfiguration...
Recent research in multi-agent systems incorporate fault tolerance concepts. However, the research does not explore the extension and implementation of such ideas for large scale parallel computing systems. The work reported in this paper investigates a swarm array computing approach, namely 'Intelligent Agents'. In the approach considered a task to be executed on a parallel computing system is decomposed...
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant real-time distributed embedded systems used for safety-critical applications. An application is modeled as a set of processes communicating by messages. Processes are mapped on computation nodes connected to the communication infrastructure. To provide resiliency against...
The shrinking of process technologies in conjunction to the manufacturing and transient faults may be abundant in high density reconfigurable architectures. Design of reliable applications on such unreliable architectures requires techniques able to provide a balance between the desired fault masking and the associated performance and power degradation. Starting from a well established solution for...
We present a fault-tolerant post-mapping resynthesis for FPGA-based designs that exploits the dual-output feature of modern FPGA architectures to improve the reliability of a mapped circuit against faults. Emerging FPGA architectures, such as 6-LUTs in Xilinx Virtex-5 and 8-input ALMs in Altera Stratix-III, have a secondary LUT output that allows access to non-occupied SRAM bits. We show that this...
As FPGA sizes and densities grow, their manufacturing yields decrease. This work looks toward reclaiming some of this lost yield. Several previous works have suggested fault aware CAD tools for intelligently routing around faults. In this work we evaluate such an approach quantitatively with respect to some standard benchmarks. We also quantify the trade-offs between performance and fault tolerance...
This paper presents a PCI-Express based platform for the analysis and evaluation of designs that combines Triple Modular Redundancy and Dynamic Reconfiguration to provide Fault Tolerance and Self-repairing capabilities. The paper presents the general architecture of the platform and exemplifies its functionality with the implementation of a Self-Repairing CAN Gateway.
Network communication algorithms development is presented in the paper, with the purpose to implement bio-inspired hardware systems which exhibit the abilities of living organisms, such as: evolution capabilities, self-healing and fault-tolerance. In the first steps of these research efforts an embryonic system with bi-dimensional FPGA-based artificial cell network is designed and tested through careful...
The ROAR Project (1997-2002)- Looking Back Nirmal R. Saxena, NVIDIA, Santa Clara, CA, USA Around 1996, the Defense Advanced Research Projects Agency (DARPA) announced the adaptive computing systems (ACS) program to focus on providing rapid adaptation and acceleration of sensor front-end signal processing algorithms using field-programmable gate array (FPGA) based computing devices and software. Stanford...
The use of commercial-of-the-shelf SRAM-based FPGA devices in space applications is not yet a reality due to concerns still existing about the device reliability; therefore, more conservative approaches based on anti-fuse FPGAs are currently preferred. The major concern about the use of such devices in space stems from their sensitivity to ionizing radiation, which may alter the content of the design...
This paper deals with reconfigurable control associated with switch failure fault tolerant converter topology for Wind Energy Conversion Systems (WECS). A typical WECS with Doubly Fed Induction Generator (DFIG) is concerned. A converter topology without any redundancy is studied. This fault tolerant topology becomes a ldquofive-legrdquo structure after switch failure detection and converter reconfiguration...
Commercial SRAM-based FPGAs have the potential to provide aerospace applications with the necessary performance to meet next generation mission requirements. However, the susceptibility of these devices to radiation in the form of single-event upsets is a significant drawback. TMR techniques are traditionally used to mitigate these effects, but with an overwhelming amount of extra area and power....
A dynamically reconfigurable on-chip multiprocessor architecture is presented, which can be adapted to changing application demands and to faults detected at run-time. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC with minimal area...
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