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New satellite communication scenarios, especially the so called ”space internet”, require new concepts of flexible satellite payloads. A reconfigurable On-Board- Processor (OBP) based on Field-Programmable Gate Array (FPGA) technology addresses the needed flexibility. FPGA based reconfigurable OBPs enable the adaption of current use cases for various applications via reconfiguration of the digital...
FPGAs provide reconfigurability and high performance for parallel applications. Modern FPGAs can be integrated in computing systems as accelerators so that they can combine with host CPU to execute offload applications. This integration puts more pressure on the fault tolerance of computing systems and the question how to improve the dependability becomes crucial. Similar to CPU-based system, checkpoint/restart...
Programmable hardware devices, specifically FPGAs, are increasingly being used in critical applications. State-of-the-art devices use SRAM memory for configuration purposes, which is very sensitive to faults. Previous studies have shown that, the vast majority of the generated errors have a high latency, and that some failures are due to the accumulation of errors. To overcome these threats, manufacturers,...
Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. However, the susceptibility of such memory cells to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is still the most accepted verification technique. This paper describes FIRED, a fault injector targeted...
Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy,...
This paper presents the method of dependability parameters improvement for systems based on unreliable components such as Field Programmable Gate Arrays (FPGAs). It combines Concurrent Error Detection (CED) techniques [4], FPGA dynamic reconfigurations and our previously designed Modified Duplex System (MDS) architecture. The methodology is developed with respect to the minimal area overhead and high...
Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated...
Product or design quality encompasses many aspects. One of them is the robustness with respect to perturbations. This robustness depends on the implementation technology, but can also be improved at design time. This paper is focused on designs implemented in SRAM-based FPGAs that are sensitive to soft errors in the configuration memory. An approach is proposed to increase the dependability with respect...
In this paper, a dependability analysis of fault tolerant systems implemented into the SRAM-based FPGA is presented. The fault tolerant architectures are based on the redundancy of functional units associated with a concurrent error detection technique which uses the principles of partial dynamic reconfiguration as a recovery mechanism from a fault occurrence. Architectures are tested by injecting...
Field Programmable Gate Arrays (FPGAs) are highly configurable programmable logic devices. They offer many benefits over traditional micro-processors such as the ability to efficiently run tasks in parallel and also highly predictable timing performance. They are becoming increasingly popular for use in the safety critical domain where predictability is essential. However, concerns about their dependability,...
A tool for managing finite state machines was developed and presented in this paper. The tool uses an algorithm of serial decomposition to perform operations on these FSMs. With the help of these operations, reduction in size of the combinational part of the circuit can be achieved, leading to smaller memory requirements. The resulting FSM implemented using an FPGA is provided with concurrent error...
This paper introduces and discusses dependability features of a Telecomm and and Telemetry subsystem designed under a Brazilian Space Program contract. The whole subsystem has been developed in a hardware description language (HDL), targeting anti-fuse programmable once FPGA devices. The discussed features include device redundancy, at hardware level, and several adopted strategies at the HDL level.
The Controller Area Network (CAN) fieldbus is a popular technology for distributed embedded system networking. Its usage spans several domains, ranging from home automation to factory control. There are, however, restrictions to its application in a specific domain: highly dependable applications. A crucial step towards CAN-based dependable systems was taken by the CAN Enhanced Layer (CANELy) architecture...
An increasing number of applications rely on embedded systems for a correct behavior or user interaction. Many of these systems are today considered critical (for safety, security ... or just for competitiveness), but cannot be expensive and often need flexibility. SRAM-based FPGAs are good candidates to implement such systems but their main disadvantage is their relatively high probability of application...
Reconfigurable many-core processors have many advantages over conventionally designed devices, such as low power consumption and very high flexibility. For an increasing number of safety-critical applications, these processors must have an ultra high dependability. This paper discusses the design and verification of an infrastructural IP, the Dependability Manager, which takes care of most essential...
This paper proposes a new reconfigurable architecture for configuration logic block (CLB) in SRAM-based FPGAs. This architecture can correct single event upset (SEU) by utilizing both triple modular redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of look-up table (LUT) in current-day SRAM-based FPGAs; moreover,...
We describe a methodology for analyzing the robustness of circuits implemented by SRAM-based FPGAs against the accumulation of soft errors within the configuration memory. A detailed analysis of the fault injection data is presented.
As SRAM-based field-programmable gate arrays (FPGAs) are introduced in safety- or mission-critical applications, the availability of suitable Electronic Design Automation (EDA) tools for predicting systems dependability becomes mandatory for designers. Nowadays designers can opt either for workload-independent EDA tools, which provide information about system's dependability disregarding the workload...
As SRAM-based FPGAs are introduced in safety- or mission-critical applications, the availability of suitable electronic design automations (EDA) tools for predicting systems dependability becomes mandatory for designers. Nowadays designers can opt either for workload-independent EDA tools, which provide information about system's dependability disregarding the workload the system is supposed to elaborate...
Embedded operating systems are becoming widely used in electronic systems for fields ranging from the mobile phone to the industrial control mechanisms. The major advantages in using embedded operating systems include the capability of adapting the electronic functionalities to several kind of applications while respecting the real-time constraints. These characteristics make them attractive also...
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