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A 16-bit fully functional one cycle RISC processor was developed for the illustration and use in computer architecture classes. It is simple enough so that it can be designed by entry level students without any prerequisites as home assignment. In addition its architecture is optimized to support the computer architecture curriculum with concrete practical hands-on experiments. The processor is subsequently...
The paper presents a formal design methodology for reconfigurable, modular digital controller logic synthesis. The project of embedded controller starts from behavioral, graphical hierarchical and concurrent state machine description in Unified Modeling Language (UML). After the hierarchical encoding of nested and concurrent superstates, the UML state machine diagram can be directly and automatically...
One of the reasons that prevents digital designers to adopt asynchronous design methodologies is the lack of high level design tools that are available for asynchronous design. Nowadays, it is quite common to use Simulink, from The Mathworks, as a modeling tool and then to synthesize the developed diagram into RTL code automatically. In the synchronous domain some tools are able to synthesize such...
Nios II is the soft-core 32 bits RISC processor of the Altera Corporation which can be implied in its FPGA. Users can design their own peripherals accord with Avalon Bus specification in Nios II system. A new design method for plus width module (PWM) peripheral is presented, which is completed by Verilog HDL. Comparing to the common PWM module, this new PWM module use the hardware units (logic elements...
We present in this paper architecture and preliminary evaluation results of a novel dual-mode processor architecture which supports queue and stack computation models in a single core. The core is highly adaptable in both functionality and configuration. It is based on a reduced bit produced order queue computation instruction set architecture and functions into Queue or Stack execution models. This...
Low density parity check (LDPC) codes are the error-correcting codes which offer huge advantages in terms of coding gain, throughput and power dissipation. Error correction algorithms are often implemented in hardware in order to ensure fast processing. The hardware implementation of LDPC decoders using traditional hardware description language (HDL) based approach is a complex and time consuming...
A new method for ADC IP integration in a mixed-signal MCU is proposed in this paper. The single conversion of ADC is controlled by three modes: software triggered mode, hardware triggered mode and PWM triggered mode. ADC and the PWM control module can work independently under software and hardware triggered mode. PWM triggered mode used for real-time monitoring is an innovation of the paper, which...
Model-based verification is extensively begin used for accelerating the development of embedded system. However, by this approach, a model and actual RTL are required to be implemented separately, which increases the time required to ensure the equivalence of virtual models and actual hardware. To reduce the costs incurred in separate implementations, we propose to directly generate RTL from verification...
Reconfigurable SoPC is an advanced component for distributed and real time applications. Co-design of HW and SW for SoPC are both in hierarchy and hybrid. For hierarchy, a SoPC application design may be concerned to C language, Assembly, Hardware Description Language HDL and PLD hardware. For hybrid, the SoPC hardware is built by HDL programming on PLD in some design level. That means the hardware...
Using RTL (Register Transfer Level) models for the verification of complex hardware designs involves reducing the state space of designs using various abstraction techniques. In this paper, we propose faster and earlier verification of hardware designs at a level of abstraction above RTL. We consider a high-level (above RTL) hardware model that uses atomic rules to describe the behavior of a design,...
For more effective software development of a microprocessor based system, a cross-simulator is helpful. To generate the simulators in a short period, we have developed the pan-simulator system with the method that the characteristic modules of the microprocessor are to be described, and linked with the prepared common simulator modules. This paper outlines the function and processing of the common...
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