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We report the demonstration of a new contact resistance reduction technology for Si:C S/D using Tellurium (Te) implant and segregation. When integrated in a novel process flow featuring a single-metal platinum-based silicide (PtSi) contact technology, independent control of SBH in n- and p-FinFETs can be achieved. A low electron SBH of 120 meV is attained for n-FinFETs with Si:C S/D using PtSi and...
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of key devices for high performance and low power advanced LSIs in the future. In addition, the heterogeneous integration of these materials with Si can provide a variety of More-than-Moore and Beyond CMOS applications, where various III-V/Ge functional devices can be co-integrated. In this presentation, we review...
This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and...
With process variability increasing in advanced processes, it becomes more challenging to diagnose or debug a low-yield problem. For finding out the root causes of a low-yield problem, currently we rely on limited process data provided by foundries or diagnosis tools and physical failure analysis (PFA). Only relying on defect diagnosis analysis and PFA is not sufficient to quickly conclude with a...
A method is developed to obtain the alloy scattering coefficients from first-principles band structure calculations. It is found that the scattering matrix can be decomposed into two additive components: a chemical part due to atomic substitution and a part due to ionic relaxation. The method is then applied to find the intra-and inter-valley electron scattering rates for substitutional carbon in...
Al/SiO2/pp+-Si metal-insulator-semiconductor (MIS) solar cell device was simulated using a comprehensive numerical model. The semiconductor layer consists of p-type Si epitaxial layer (base) which is deposited on p+-Si(001) substrate. The doping profile in the base layer was chosen to be arbitrary with different doping gradients. The effect of doping profile in the base layer and substrate was studied...
This paper describes a versatile and reliable wafer-level hermetic packaging technology using an anodically-bondable low temperature cofired ceramic (LTCC) wafer, in which electrical feedthroughs and passive components can be embedded. The hermeticity of vacuum-sealed cavities was confirmed after 3000 cycles of heat shock (-40°C/+150°C, 30 min/30 min) by diaphragm method. The width of seal rings necessary...
This paper reports an electromagnetic shielded cantilever-tip microwave-probe for conductive-property imaging at micro/nano surface-area. Equipped with an ultra-sharp tip apex (<;50 nm), the probe features small conducting path resistance of Rs<;5Ω and conducting path-to ground capacitance of Ctip≈1pF. These optimal-designed parameters facilitate satisfactory spatial resolution and microwave-signal...
We report a novel microfluidic surface-enhanced Raman scattering (SERS) device, which is achieved by bonding a polydimethylsiloxane cap with a microchannel structure onto an SERS-active substrate composed of noble-metal covered silicon nanopillar forests. The silicon nanopillar forests are fabricated by using nanomaterial dots, which are introduced in oxygen-plasma bombardment of photoresist, as etching...
This study presents a novel fully-differential capacitive sensing accelerometer design consisting of glass proof-mass and Si-vias. The accelerometer with glass proof-mass has three merits, (1) the insulation glass proof-mass and conducting Si vias enable the gap-closing fully-differential electrodes design, (2) the electrical routings on insulation glass proof-mass can reduce parasitic capacitance,...
This paper introduces a novel design of high current field emitters based on unique pin structures with a ball shaped tip. Our ball-tip pins provide relatively large surface area at the tip and increase the field enhancement factor regardless of dimension of the pin base. The ball-tip pins turn out to produce higher field emission current than that from the generic sharp-tip pins due to the significantly...
We propose optical switches in which the heater is fabricated directly on the slab region of the rib waveguide. Two types of Heater-on-Slab (HoS) switches were investigated. In the first type, the silicon slab regions are doped highly to form the heaters. For this type of switches, the switching power is ~85 mW and the switching time is ~27 μs. In the second type, a strip of metal in direct contact...
This paper presents the analyses of 3D (3 Dimensional) stacked on-chip PDN (Power Distribution Network) impedances, which are composed with on-chip PDNs and TSV (Through Silicon Via) interconnections, and show the various features depending on on-chip PDN designs and 3D stacked chip configurations. Multi-stacked on-chip PDNs with very large capacitances interacting with even very small inductive TSV...
We propose a step-structure hybrid plasmon waveguide on silicon-on-insulator (SOI). The metal step provides an additional degree of freedom to trade-off between mode confinement and attenuation. The achieved nonlinearity is 2-3 orders larger than that of conventional silicon waveguide. We then design an ultra-compact, broadband optical parametric amplifier (OPA) using such a structure.
The paper discusses the recent achievements in the development of chips with integrated sensing of biomolecules. In particular, it focuses on integrated sensing electrodes on silicon and presents innovative solutions for the enhanced robustness of the electrodes towards cleaning processes and electrolytes. In this study, a microfabrication technology for 3D-integrated disposable chip layers that enables...
Solar cells consisting of extremely uniform and ordered large-area arrays of silicon micropillars are fabricated using metal-assisted chemical etching. Micropillar diameter, pitch, height, and core-shell doping profiles are optimized for light trapping and carrier collection.
We present the reliabilities in compressively strained SiGe channel pMOSFETs. A Si capping layer in SiGe channel pMOSFETs improved the negative bias temperature instability (NBTI) without device performance degradation. Also, the Si capped device exhibits the better NBTI reliability than the Si channel device. Because a Si capped structure forms the double barrier layer in the interface, it is the...
This paper presents an all-passive, 4-element, phased-array beamformer based on a differential, reflection-type phase shifter (RTPS) operating in the 60GHz band. The RTPS consists of a differential, vertically-coupled, coupled-line hybrid and variable, parallel-LC, resonant, reflective loads, both of which enable low-loss millimeter-wave operation. The design considerations for a silicon-based implementation...
A demonstration of VFB/Vth tuning has been conducted by optimized annealing in oxygen ambient for direct contact of high-k with Si gate stacks. The amount of oxygen atoms has been controlled by optimized annealing temperature and the thickness of the gate electrode. The shift in VFB has been confirmed irrespective of gate dielectric materials and the thickness. The Vth of pMOSFET can be controlled...
The charge plasma (CP) diode is a novel silicon rectifier using Schottky barriers, to circumvent the requirement for doping and related problems when small device dimensions are used. We present a model for the DC current voltage characteristics and verify this using device simulations. The model revealed an exponential dependence of the current on the metal work functions. And approximate linear...
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