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In this paper, we aim at increasing the strength of weak arbiter physical unclonable function (APUF) which are vulnerable to modeling attacks because of low uniqueness and randomness. We propose a unique technique which takes n × 1 challenge-response pairs (CRPs) from APUF and combines them with ring oscillators (ROs) implemented on the same FPGA to get n × n CRPs. We claim the proposed technique...
This paper presents polymorphic logic gates for hardware security using giant spin Hall effect (GSHE) devices in which electron spin is the information token. Compared to existing CMOS (charge-based) IP protection and camouflaging security techniques, the proposed GSHE logic offers significant reduction in implementation area as well as power dissipation. Based on the Monte-Carlo simulation of stochastic...
Due to globalization of IC, hardware is defenseless to new sorts of assaults, for example, counterfeiting, figuring out and IP piracy. Logic locking technique is used for the hardware security. Logic locking conceals the functionality and implementation of a design by inserting additional gates into the original design. The gates inserted for the locking are called key-gates. To display its correct...
Physical Unclonable Function (PUF) has now become a core lightweight hardware-intrinsic cryptographic primitive for device identification and authentication to secure edge computing in Internet of Things (IoT). The main challenge in most delay-based PUF implementations is the rival of response uniqueness and reliability. Due to routing constraint, implementation of delay-based strong PUF on FPGA tends...
Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. If faults happen in PUF during manufacturing, the security of whole chip will be threatened. Fault diagnosis plays an important role in the yield learning process. However, since different manufactured PUFs with the same design have different Challenge-Response Pairs (CRPs), which cannot be predicted,...
In the last decade, networks-on-chip (NoC) were proposed as a potential solution to alleviate interconnect challenges posed by bus- or crossbar-based interconnects. In this context, the principal NoC challenges have been for several years on designing reliable and efficient NoC architectures. Today, NoC have found their way on several commercial applications and products indeed, but recently they...
A major issue of present age system on chip (SoC) designing is meeting of stringent time to market deadlines along with the reduction of various challenges faced during design. A significant strategy adopted in tackling such a problem is to procure different components or IPs (intellectual properties) of the SoC from different third party IP vendors (3PIPs). Such a technique targets independent working...
The Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. The strong PUFs with numerous Challenge-Response Pairs (CRPs), such as various arbiter PUFs, mirror current PUF, and voltage transfer PUF, are severely threatened by the machine learning based modeling attacks. To handle this issue, we propose the Physical Unclonable Function with Randomized challenge...
Hardware Trojans can be inserted by an adversary at any phase of IC manufacturing. In this paper, a methodology is proposed to detect Trojans inserted after design sign-off i.e the Trojan insertion occurs at layout level. In such attack models, golden IC are not always available in all cases, thus requiring golden IC free detection methodologies. This work exploits the concept of symmetric path delays...
In this work we propose a Ring Oscillator PUF focused on the variability of the duty cycle instead of measuring the output frequency deviations. To achieve this goal, we replace the common ring oscillators, whose outputs are clock signals of 50% duty cycle, for ring oscillators with an asymmetric structure. The asymmetry confers the ability to configure the duty cycle of each individual node. Through...
Data-plane fault localization enhances network availability and reliability by enabling localization and circumvention of malicious entities on a network path. Algorithms for data-plane fault localization exist for intra-domain settings, however, the per-flow or per-source state required at intermediate routers makes them prohibitively expensive in inter-domain settings. We present Faultprints, the...
Physical unclonable functions (PUFs) utilize manufacturing variations of circuit elements to produce unpredictable response to any challenge vector. The attack on PUF aims to predict the PUF response to all challenge vectors while only a small number of challenge-response pairs (CRPs) are known. The target PUFs in this paper include the Arbiter PUF (ArbPUF) and the Memristor Crossbar PUF (MXbarPUF)...
This paper presents a method to protect digital signal processing (DSP) circuits through obfuscation by using high-level transformations. The goal is to design DSP circuits that are harder to reverse engineer. A design flow is introduced to get obfuscated circuits for digital signal processing (DSP) applications using high-level transformations. A secure reconfigurable switch design is incorporated...
The most valuable element of biometric security systems are the personal features of its users. Characteristics of individuals are unique and must be protected. We focus in this paper on methods of protection of user identity in systems based on keystroking. Our approach assumes giving minimal information to adversaries and the best responsiveness of the system regardless of user representation or...
We are moving into an era where large SoCs will have a portfolio of different kinds of cores and accelerators. Many of these computational elements might be designed by third parties. In this setting, it is beneficial to collect accurate runtime information such that we can diagnose performance problems, verify and report correctness issues, and collect usage scenarios of third party hardware. This...
Detecting error or producing correct output is the primary function of a fault secured system. In the context of multi-cycle transient faults, design space exploration (DSE) of an optimal fault secured datapath based on user constraints of area and delay during high level synthesis (HLS) is considered notorious. This is derived from the fact that generation of a user budget bounded multi-cycle transient...
Fault security indicates ability to provide error detection or fetching the correct output. Generation (design space exploration (DSE)) of an optimal fault secured datapath structure based on user power-delay budget during high level synthesis (HLS) in the context k-cycle transient fault is considered an intractable problem. This is due to the fact that for every type of candidate design solution...
In applications such as nuclear power plant, space and military, safety critical systems play an important role, where security is one of the crucial design parameters. Similar to software Trojans (virus), Hardware Trojans (HT) are raising security concerns in recent years. HTs are malicious additions or modifications to existing circuit elements which are implemented either as always on or triggered...
Computer-aided design (CAD), in its quest to facilitate new design revolutions, is again on the brink of changing its scope. Following both historical and recent technological and application trends, one can identify several emerging research and development directions in which CAD approaches and techniques may have major impacts. Among them, due to the potential to fundamentally alter everyday life...
Physical Unclonable Functions (PUF) are of increasing importance due to their many hardware security applications including chip fingerprinting, metering, authentication, anti-counterfeiting, and supply-chain tracing, e.g., DARPA SHIELD. This paper presents BIST-PUF, the first built-in-self-test (BIST) methodology for online evaluation of weak and strong PUFs. BIST-PUF provides a paradigm shift in...
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