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Soft errors in the configuration memory of SRAM-based FPGAs cause significant and remanent application disturbances. However, classical mitigation techniques based on massive redundancy are too costly for most applications. The method presented in this paper is based on selective redundancy in partially used LUTs. It can be applied so that no hardware is added at the system level and it has been automated...
Packet Classification involves matching information from a packet's header to a set of rules in a database in order to determine the manner in which the packet should be processed by network processors. The PCIU algorithm is a novel classification algorithm which improves upon previously published techniques in the literature. The main features of the PCIU algorithm are the low pre-processing time...
While the computational core is becoming faster and faster, the communication efficiency between the processors has become a bottleneck which limits the performance of multiprocessor system-on-chip (MPSoC). This paper focuses on design and implementation of AXI bus protocol-based MPSoC architecture. Firstly, the RTL models of 4 NIOS II processors using AXI communication architecture are developed...
The advance in FPGA technology allowed embedding different types of resources on a single chip. These resources range from a simple look-up table to a complete processor. The resources available on the FPGA fabric allow building various hardware systems for different applications with several trade-offs in terms of performance and power consumption. This paper proposes six different architectures...
Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, the memory access conflicts caused by multiple memory...
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