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In this paper, we present a FPGA implementation of face detection hardware (HW) and also address face recognition software (SW) on virtual platform. We apply very deeply-cascaded classifier which is composed of heterogeneous feature-classifiers to capture various characteristics of images. We use 2 step classifiers, the first searches for the coarse features and the second for the fine features. Both...
Although femtocell can confer various benefits to both operators and users, many technical issues, such as interference coordination, network synchronization, self-configuration, and self-optimization must be considered to effectively deploy femtocells in real environments. In this article, we develop a system-level simulator in order to evaluate performance of long-term evolution (LTE)-femtocell...
This paper presents a design of a turbo decoder for advanced terrestrial DMB(AT-DMB) baseband receiver SoC. The turbo decoder uses the max-log-map algorithm with simple min function. It features an interleaver address generator that computes the interleaved addresses for four block sizes enabling it to quickly switch context to support different data services. The decoder is integrated to the AT-DMB...
This paper describes the implementation of digital audio effect SoC (system on chip) which integrates the embedded DSP core, audio codec IP, a number of peripheral blocks and various audio effect algorithms. The audio effect SoC is developed by a software and hardware co-design method. The embedded DSP and some dedicated hardware blocks are developed as a hardware design while the audio effect algorithms...
The advancement of process technology enables the integration of multiple cores featuring the parallel processing with low operating energy and efficient resource utilization in embedded media processors. We propose mobile media processor SoC integrating RISC core and quad-core data processing engines with shared array of memory modules. The implicative dynamic parallel programming model dynamically...
The advancement of process technology enables the integration of multiple cores featuring parallel processing. The requirement of extensive memory bandwidth puts a major performance bottleneck in multi-core architectures for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions required by multiple cores, memory access conflicts...
The TETRA (terrestrial trunked radio) speech codec is mandatory for all TETRA mobiles and networks. This paper presents the cost-effective implementation of the TETRA speech codec using the primitive functions of the compiler for the 16 bit fixed-point eDSP (embedded DSP), which was developed by ETRI for the purpose of use in various SoCs. Generally, the simple implementation of the speech codec is...
Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, the memory access conflicts caused by multiple memory...
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