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With the coming of ‘Big Data‘ era, high-energy-efficiency database is demanded for the Internet of things (IoT) application scenarios. The emerging Resistive Random Access Memory (RRAM) has been considered as an energy-efficient replacement of DRAM for next-generation main memory. In this paper, we propose an RRAM-based SQL query unit with process-in-memory characteristic. A storage structure for...
Memories are currently a real bottleneck to design high speed and energy-efficient systems-on-chip. A significant increase of the performance gap between processors and memories is observed. On the other hand, an important proportion of total power is spent on memory systems due to the increasing trend of embedding volatile memory into systems-on-chip. For these reasons, STT-MRAM (Spin-Transfer Torque...
An energy-efficient and high-speed stereo matching processor is proposed for smart mobile devices with proposed stereo SRAM (S-SRAM) and independent regional integral cost (IRIC). Cost generation unit (CGU) with the proposed S-SRAM reduces 63.2% of CGU power consumption. The proposed IRIC enables cost aggregation unit (CAU) to obtain 6.4× of speed and 12.3% of the power reduction of CAU with pipelined...
Highly reliable Physical Unclonable Functions (PUF) based on 28nm Split-Gate MONOS (SG-MONOS) embedded flash memory is developed for hardware security applications. In this paper, we investigate wide range tolerance on applied voltage, temperature and aging influence for basic PUF characteristics utilizing SG-MONOS initial Vt variation. High-temperature stable PUF at the junction temperature (Tj)...
Spin-Transfer Torque RAM (STT-RAM) has a higher density than SRAM and non-volatility, and is expected to be used as the last-level cache (LLC) of a microprocessor. One technical issue is that, since the energy cost of write access requests for an STT-RAM LLC is expensive, the total energy consumption of the STT-RAM LLC may increase for some write-intensive applications. Therefore, this paper proposes...
The randomness and unpredictability of Random Telegraph Noise (RTN) of 16nm FinFET Dielectric (FIND) RRAM is firstly implemented to Time-Contingent Physical Unclonable Function (PUF) application. A novel 3D Time-Contingent Physical Unclonable Function (TC-PUF) realized by 1Kbit 16nm FinFET Dielectric (FIND) RRAM has been newly proposed and demonstrated on a pure 16nm FinFET CMOS logic technology....
Noise in the image are random variations in intensity due to intrinsic or extrinsic sources. This paper proposes a high throughput Fixed Point Discrete Kalman filter (DKF) architecture for denoising images with additive white Gaussian noise (AWGN) at real-time. A linearized state model based on neighbor pixel similarity is used for improving the PSNR of the noisy image. A 5-stage two parallel bi-functional...
We have implemented a flexible User Defined Operator (UDO) for labeling connected components of a binary mask expressed as an array in SciDB, a parallel distributed database management system based on the array data model. This UDO is able to process very large multidimensional arrays by exploiting SciDB's memory management mechanism that efficiently manipulates arrays whose memory requirements far...
In this paper, we introduce a computational method for constructing networks based on reverse phase protein array (RPPA) data to identify complex patterns in protein signaling. The method is applied to phosphoproteomic profiles of basal expression and activation/phosphorylation of 76 key signaling proteins in three breast cancer cell lines (MCF7, LCC1, and LCC9). Temporal RPPA data are acquired at...
Microprocessor system is a must know subject in electrical engineering. Despite of learning through simulation, student, especially in polytechnic, have to be more involved in the hands on practice. Z80 is one of the simplest microprocessor system for studied. Many of existing Z80 learning board came with tons of user friendly interfaces, such as a keypad and alphanumerical LCD, however, the most...
Energy and power consumption are major limitations to continued scaling of computing systems. Inexactness where the quality of the solution can be traded for energy savings has been proposed as a counterintuitive approach to overcoming those limitation. However, in the past, inexactness has been necessitated the need for highly customized or specialized hardware. In order to move away from customization,...
Approximate memory is a promising technology for emerging recognition, mining and vision applications. These applications require the processing of large volumes of data to achieve energy-efficiency with negligible accuracy loss. This paper proposes a multi-level approximate memory architecture based on data significance analysis. In this architecture, a memory array is divided into several separated...
For the first time, by using a novel multiple individual bank sensing/writing and a memory bank interleave design, we demonstrate a double date rate 2 (DDR2) DRAM like interface phase-change memory (PCM) for M-type storage class memory applications . The write and read bandwidth is equal to 533MB/s, and the random read latency is 37.5ns, while the write latency is 11.25ns supporting a random write...
The problem of increasing the coefficient of technical readiness of memory module, the value of which increases with decreasing of control system recovery time in case of failure of its constituent units, is solved. The proposed structure of the memory module with built-in self-test and restore functionality that will allow auto-replacing bits of data of the main memory cell array, in which there...
Spin Transfer Torque Magnetoresistive RAM (STTMRAM) has been recently deemed as one promising main memory alternative for high-end mobile processors. With process technology scaling, the amplitude of write current approaches that of read current in deep sub-micrometer STT-MRAM arrays. As a result, read disturbance errors (RDEs) emerge. Both high current restore required (HCRR) reads and low current...
Reconstructive signal processing algorithms involve complex computations, where matrix inversion is one of the most complex operations required by several signal processing applications (e.g., image processing or MIMO systems in wireless communication transmission). Currently, QR decomposition implemented with systolic arrays have been proposed in recent studies; however, the internal structure of...
The Internet of Things (IoT) applies the sensors and MCUs on various machines, devices and equipment, and connect them through internet. The emerging non-volatile memory, Resistive Random Access Memory (ReRAM) is suitable for the sensor data storage because of the low voltage and low power program operation. In this paper, the proposed 0. 6 V operation, 0.27 mm2 die size boost converter is demonstrated...
Digital microfluidic biochips are revolutionary solutions towards automation of bio-chemistry procedures. This technology offers promising improvements in terms of experiment time, consumption of experiment materials and reconfigurability. This paper presents a novel pin-constrained digital microfluidic biochip architecture; the proposed design is formed by placing appropriate number of fundamental...
In this paper, advanced channel signal processing schemes are proposed for multi-track or multi-wordline read architecture in the future hard disk drive and NAND flash memory systems. As the capacity increases with aggressive scaling of the data bit or memory cell, the interference or coupling between neighboring information causes severe inter-track (ITI) or inter-cell interference (ICI), and advanced...
Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose...
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