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This paper presents an analysis of different alternatives for the realization of a VLSI cell in a nonlinear neuronal array, based on a simplicial piecewise linear (PWL) operation. Depending on the type of existing design constraints, namely, speed or density, different bus sizes can be used to broadcast the parameters stored in the memory, and in addition, row and column operations can be serialized...
In this paper, we introduce a constraint programming-based approach for optimization of routing and reconfiguration overhead for a class of reconfigurable processor array architectures called weakly programmable. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for optimal routing of data between processors...
In this paper, we introduce a constraint programming-based approach for the optimization of area and of reconfiguration time for communication networks for a class of regular 2D reconfigurable processor array architectures. For a given set of different algorithms the execution of which is supposed to be switched upon request at run-time, we provide static solutions for the optimal routing of data...
In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
This paper presents a programmable interconnection network for a novel multi-reticle integrated circuit providing a reconfigurable circuit board for rapid system prototyping. This multi-dimensional mesh grid network, called WaferNettrade, can actively interconnect any pair of pins of integrated circuits deposited on the configurable system board. Two crossbar architectures are implemented and compared,...
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