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A novel approach for the implementation of a field programmable embryonic cell is proposed. This is inspired from the concept of cloning used by biological cells to grow a bigger organism. An exemplary full adder and multiplier circuit evolution is simulated using Verilog and verified. An automated generation of configuration data for the embryonic cells from a behavioral description of the overall...
The signal and image processing algorithm use multiplication as one of the basic arithmetic operation. So the efficient implementation of multiplier is always a challenge. The present work describes a method to build a faster array multiplier by delay optimized inter connection globally. The proposed array multiplier architecture performance in terms of delay and hardware is compared with conventional...
In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low dynamic power consumption...
Low power multipliers with high clock frequencies play an important role in today's digital signal processing. In this work, the performance analysis of Wallace-tree, Array and Baugh-Wooley multiplier architectures is carried out. Physical verification of all the sub-blocks is performed using HSpice to check their functionality and to optimize for low power by using transistor sizing. The layouts...
This paper introduces a reconfigurable computing cell architecture for pipelined and systolic datapaths in the mixed grained reconfigurable coprocessor array system (MiGCop). The cell is efficiently capable of building scalable parallel-parallel, serial-parallel, and serial-serial signed multipliers. Several cells can be combined to form a reconfigurable coprocessor that is tightly coupled with clusters...
Microprocessor and DSP are optimized to perform operations on data having the same size of native wordlength. Their performances decrease when shorter data must be processed. In fact, operations on a short data have the same complexity native wordlength data and data resources are not fully exploited. Recently different solutions have been proposed to overcome this problem. Great attention has been...
In this paper a new technique for the design of combinational circuits for low power is introduced. According to this technique, we bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption...
An 8 ?? 8 bit NMOS multiplier test chip for image processing systems has been realized on the basis of a newly designed carry save adder cell, a multiplication rate of 3.3 108 1/sec (fc = 330 MHz) being achieved.
This paper presents a parameterization concept for the automatic layout generation of multipliers in digital signal processing. Based on a hierarchical cell design methodology the layout of parameterized two's complement bit-parallel multipliers can automatically be generated according to any desired wordwidth of multiplicand and multiplier. Additionally the product can be rounded or truncated to...
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