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A bus controlled power driver circuit for output currents up to 250 mA and output voltages up to 60 V using I2L logic has been realized. By introducing "partial n+-deep shielding" proper function of the I2L gates even in lightly doped epilayers (9epi = 4.5 ??cm) has been achieved.
An Instrumentation Amplifier is described which achieves a gain-bandwidth product of 400 MHz at a gain of 1000 while remaining stable at unity gain. It also features FET inputs making it highly useful in multiplexed acquisition systems. The circuit is built on a Bi-FET/Thin Film bipolar process with no special high speed requirements.
A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law I-V characteristics of the MOS transistor. Linearity is better then 0.14 % for an output swing of 36 % of the supply current. The bandwidth is from de to above 1 MHz.
A wideband voltage-current converter circuit with nonlinearity-error compensation has been developed. Bandwidth is 100 MHz (??3dB) or 30 MHz (??1%). The circuit was realized with a new bipolar cell-based semicustom array intended for use in training as well as for industrial prototyping and custom IC production.
An embedded language in Pascal is used to describe hierarchical module and connection generators. Layout and simulation models are created simultaneously observing user defined constraints. Two chips of different type of architecture show the feasibility of this concept.
A symmetric FIR filter, intended for oversampling as part of a video decoder, has been designed, and implemented in a 3.15 NMOS technology according to two opposite methodologies : an optimized handpacked design, vs a "module compiler" approach. The latter, which is a general FIR filter generator, is described, the circuit realizations are presented with a comparison and evaluation of these...
An IC which performs DSV error monitoring and clock and data fail detection in an optical fibre transmission system is described. The circuit makes use of cells from a high speed logic cell library integrated with specialised analogue functions to achieve combined analogue and digital operation at 680Mb/s.
A monolithic dual high-speed 16 bit D/A converter is described. Each converter can be used without extra sample-and-hold or deglitcher circuitry at sampling speeds up to 200 kHz. The converter has a differential linearity of typically 0.5 LSB over a temperature range of -20 to +70??C.
An addressable controller had to be developed for a large scale advertising display panel numbering some 64000 high-output light-emitting diodes. Custom integration in standard bipolar technology provided an answer to the system design challenge. An on-chip PROM solves the addressing problem while circuit design minimizes power consumption and affords protection against LED failure. This chip illustrates...
A VLSI layout compactor, ADULTS-L, is proposed. It can deal with both real physical mask patterns and symbolic patterns for VLSI layout. It features hierarchical design support and process independence. This paper describes a system configuration, an algorithm and a layout result of ADULTS-L. The main features of ADULTS-L are as follows; 1. It is a grid free layout compactor. 2. It can support a hierarchical...
This paper presents a general and efficient tool for the computer-aided nominal design of integrated circuits. The design method is based on an interactive optimization approach and on a soohisticated interface to the circuit level simulation package SPICE providing a high level tool for the task of designing cells at transistor level. The efficiency of the design tool proposed is demonstrated by...
This paper describes the integration of a new tool for testability measurement and improvement into a design system for integrated circuits. The involved design system, CADDY (Carlsruhe Digital Design System), uses a functional description of a circuit written in a PASCAL like language and synthesizes a list of nets and real logical components. In this resulting structure all storing elements are...
A 12ns/350mw 16Kb ECL compatible RAM with bipolar ECL inpur/output buffers has been developed by using 2??m polyside gate CMOS technology which has bipolar transistors with 3GHz cut-off frequency on the same chip.
The need for high density, low power and fast CMOS EPROM has been established by the evolution of high performance circuits such as microprocessors. This paper will discuss A 256K CMOS EPROM utilizing 2 UM design rules technology. The word organization is 32K words X 8. The cell size is 54.4 UM2 and the die size is 29.6 MM2 including 4 extra rows and 2 extra columns. To reduce power consumption address...
This paper presents several techniques for optimizing large monoplane PLAs (which contain mixed I/O lines). The different approaches used to optimize the area of these PLAs involve several VLSI topological optimization strategies. Compaction by cutting and reorganizing the product-term lines in order to reduce the number of rows in the entire PLA, is the main approach. The layout generation of an...
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