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Nowadays some High Level Synthesis (HLS) tools are introduced which are able to generate Hardware Description Language (HDL) codes from high level floating point arithmetic expressions for implementation on FPGAs. Before this conversion, changing the form of high level expressions usually leads to significant improvements in the final implementation in terms of accuracy, resource usage and latency...
CORDIC or CO-ordinate Rotation Digital Computer is a fast, simple, coherent and powerful algorithm which is used for diversified Digital Signal Processing applications. In pursuance of speed and accuracy requirements of todays applications, we put forward variable iterations CORDIC algorithm. In this algorithm, to boost speed we can lessen number of iterations in CORDIC algorithm for specific accuracy...
The main aim of this paper is to design a parameterized 32 bit floating point multiplier which is based on IEEE 754-2008 binary interchange format. The proposed work is capable of checking overflow and underflow using corresponding flags by flagger circuit. In this design rounding modes are also considered based on the two bit control signal provided as input such as round to nearest even, round to...
Maximum a posteriori probability inference algorithms for Markov Random Field are widely used in many applications, such as computer vision and machine learning. Sequential tree-reweighted message passing (TRW-S) is an inference algorithm which shows good quality in finding optimal solutions. However, the performance of TRW-S in software cannot meet the requirements of many real-time applications,...
The Hough Transform is a pattern recognition tool commonly used in many image processing algorithms for detecting straight lines. Hough's original formulation of this transform, based on Cartesian coordinates, could not detect vertical lines, and thus it has become common to use Duda and Hart's approach, based on the Radon Transform, which uses polar coordinates and trigonometric functions. For a...
CORDIC algorithms have long been used in digital signal processing for calculating trigonometric, hyperbolic, logarithmic and other transcendental functions. The algorithm requires only shift and add operations and this simplicity encourages its implementation in hardware. Traditional CORDIC architectures have focused on radix-2 implementations because of their higher accuracy. However these architectures...
Stereo matching is a vital task in several emerging embedded vision applications requiring high-quality depth computation and real-time frame-rate. Although several stereo matching dedicated-hardware systems have been proposed in recent years, only few of them focus on balancing accuracy and speed. This paper proposes a hardware-based stereo matching architecture that aims to provide high accuracy...
<?Pub Dtl?>This paper presents an FPGA implementation of an algorithm, previously published, for the the reconstruction of cosmic rays’ trajectories and the determination of the time of arrival and velocity of the particles. The accuracy and precision issues of the algorithm have been analyzed to propose a suitable implementation. Thus, a 32-bit fixed-point format has been used for the representation...
Ahstract-Set-wise floating point accumulation is a fundamental operation in scientific computing, but it presents design challenges such as data hazard between the output and input of the deeply pipelined floating point adder and numerical accuracy of results. Streaming reduction architectures on FPGAs generally do not consider the floating point error, which can become a significant factor due to...
An efficient hardware implementation of Gaussian Random Number (GRN) generator based upon Box-Muller (BM) and CORDIC algorithms is presented. We will illustrate a novel hardware architecture with flexible design space that unifies the two algorithms. A major advantage of this work is that unlike any of the previously reported architectures, it is possible to eliminate hardware multipliers and memory...
The MEMOCODE 2013 design contest problem is stereo matching. Given a stereo image pair (i.e., a left image and a right image), the challenge is to infer the depth information (i.e., third dimension) for each pixel in the image utilizing belief propagation algorithm. Contestants were given a month to develop a fast and/or cost-effective system for stereo matching. From a total of eight participating...
This paper presents a fast-convergence and robust adaptive step size equalization approach for a 14-bit 200MS/s hybrid pipeline-SAR analog-to-digital converters (ADC). The proposed calibration approach corrects errors not only from capacitor mismatch, gain error, op amp nonlinearity, and comparator offset, but also the reference DAC error and inter-stage mismatch errors. It is robust and permits higher...
This article describes a new approach for higher radix butterflies suitable for pipeline implementation. Based on the butterfly computation introduced by Cooley-Tukey [1], we will introduce a novel approach for the Discrete Fourier Transform (DFT) factorization, by redefining the butterfly computation, which is more suitable for efficient VLSI implementation. The proposed factorization motivated us...
High performance implementations of unary functions are important in many applications e.g. in the wireless communication area. This paper shows the development and VLSI implementation of unary functions like the logarithmic and exponential function, by using a novel approximation methodology based on parabolic synthesis, which is compared to the well known CORDIC algorithm. Both designs are synthesized...
Rapid advances in multichannel neural signal recording technologies in recent years have spawned broad applications in neuro-prostheses and neuro-rehabilitation. The dramatic increase in data bandwidth and volume associated with multichannel recording requires a significant computational effort which presents major design challenges for brain-machine interface (BMI) system in terms of power dissipation...
An instrument based on FPGA to determine in few periods the fundamental frequency of a electrical grid signal has been realized. A classic algorithm as Curve Fitting Algorithm has been analyzed and modified to reduce its numerical complexity. This paper shows how the floating point software algorithm has been implemented on hardware architecture in fixed point representation, controlling the accuracy.
As the feature size of FPGA shrinks to nanometers, soft errors increasingly become an important concern for SRAM-based FPGAs. Without consideration of the application level impact, existing reliability-oriented placement and routing approaches analyze soft error rate (SER) only at the physical level, consequently completing the design with suboptimal soft error mitigation. Our analysis shows that...
In this paper, a new IC has been proposed for detection of bleeding region in the GI tract, to be implemented inside the capsule endoscope. In this design, firstly, by combining the image characteristics of RGB and HSI color image spaces as well as making the algorithm adaptive to image luminance, the most optimal algorithm considering the bleeding detection evaluation parameters, have been proposed;...
A North Finder consisting of one Fiber Optic Gyroscope (FOG) and two accelerometers is designed to meet the requirements of low-cost, fast and high-precision. Two-position North-seeking scheme for the FOG North-Finder is presented, and a high-performance north-seeking computer using Digital Signal Processing (DSP) and Field-Programmable Gate Array (FPGA) is designed. Precision mechanical locking device...
To improve the performance of silicon micro-gyroscope (SMG), a digital measurement and control scheme of SMG with symmetrical and decoupled structure is presented. The system was constructed with a high-performance FPGA hardware core and several precision peripherals such as analog and digital hybrid conditioning circuits. Some key modules and algorithm realization including the closed-loop drive...
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