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The overall system cost and other considerations require that processors deliver high performance within a given power budget. Pipelining and supply voltage, both affect the performance and power consumption. Therefore, pipelining depth can be varied simultaneously with appropriate adjustments in supply voltage so as to keep power consumption constant while affecting performance of a processor. This...
We propose a Multi-Vdd Fine-Grained VariablePipeline (MVFG-VP) router in order to reduce power consumptionof Network-on-Chips (NoCs) designed for many-coreprocessors. MVFG-VP router adjusts its pipeline depth (i.e., communication latency) and supply voltage level of each inputand output channel independently. Unlike Dynamic Voltageand Frequency Scaling (DVFS) routers, MVFG-VP routersshare the same...
With the expanding of large computing platforms and the increasing of on chip transistors, power consumption becomes a significant problem. Many methods are proposed in different design levels to solve the problem. In this paper, we introduce asynchronous technique to an IEEE-754 double-precision floating-point multiplier aiming to reduce its power consumption. The control path of the asynchronous...
In recent years, many research results have discussed the mixed static-domino high-speed circuit. However, most research neglects to discuss how to implement their results. Silicon Intellectual Property plays very important roles in the design of current complex integrated circuits. In this paper, we construct a new pipeline mixed static-domino high-speed circuit synthesized methodology. The cell-based...
A 12-bit 60 MS/s SHA-less opamp sharing pipeline ADC utilizing switch-embedded dual-input current-reused opamp is presented in this paper. The proposed opamp sharing technique reduces the power consumption without suffering from memory effect. Two-phase overlapping clocks are proposed to ensure analog transistors in the common-mode feedback (CMFB) loop to always work in saturation thus avoiding common...
The de-synchronization methodology, which directly converts a synchronous circuit into an asynchronous counterpart according to the physical structure of pipelines, is very popular for its simplicity. However, the simplicity of the design methodology also introduces some power redundancy and performance reduction to de-synchronized circuits. This paper firstly investigates the influence of actual...
Since the onset of pipelined processors, balancing the delay of the microarchitectural pipeline stages such that each microarchitectural pipeline stage has an equal delay has been a primary design objective, as it maximizes instruction throughput. Unfortunately, this causes significant energy inefficiency in processors, as each microarchitectural pipeline stage gets the same amount of time to complete,...
We propose a multi-voltage (multi-Vdd) variable pipeline router to reduce the power consumption of Network-on-Chips (NoCs) designed for chip multi-processors (CMPs). Our multi-Vdd variable pipeline router adjusts its pipeline depth (i.e., communication latency) and supply voltage level in response to the applied workload. Unlike dynamic voltage and frequency scaling (DVFS) routers, the operating frequency...
In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques...
With the ever increasing needs of power aware architecture and circuit design in recent years, how to reduce the power consumption of processors without sacrificing performance has become an important issue. In this paper, we propose a new method for low power branch prediction-Hedging Filter, which combines filtering scheme reducing dynamic power consumption with hedging prediction mechanism lowering...
With the number of processor cores increasing in chip multi-processors (CMPs) and global wire delays increasing, networks on chip have been gaining wide acceptance for on-chip inter-core communication. This paper introduces a low latency Dynamic Virtual Output Queues Router (DVOQR), which can reduce the router latency to two cycles by leveraging look-ahead routing computation and virtual output address...
In this paper, we propose a new scheme for packet-switched bufferless Networks-on-Chip (NoCs). The goal is to reduce the area and power consumption while providing high performance. In the proposed scheme, we develop a new bufferless routing algorithm. Extensive cycle-accurate simulations have been conducted to show that the proposed scheme delivers a superior performance compared to both traditional...
In this paper, a dynamic timing control technique employing a time-borrowing flip-flop with a time-borrowing detection and a clock shifter is presented to prevent timing errors of a system with a minimized performance penalty. The proposed flip-flop allows time borrowing during a time-borrowing window (TBW) on critical paths and generates a time-borrowing detection signal used by the clock shifter...
This work introduces a simple, background offset cancellation scheme for zero-crossing based circuits (ZCBC). The ZCBC architecture has been proposed as an alternative to op-amp based analog to digital converts (ADC) because it does not suffer from the gain, stability, and settling time trade off. However, offset remains as a challenge. This work demonstrates an input offset cancellation scheme that...
In the past years dynamic voltage and frequency scaling (DVFS) has been an effective technique that allowed microprocessors to match a predefined power budget. However, as process technology shrinks, DVFS becomes less effective (because of the increasing leakage power) and it is getting closer to a point where DVFS won't be useful at all (when static power exceeds dynamic power). In this paper we...
This paper presents a new study over logics circuit operation in subthreshold and threshold region. CMOS circuit model operation logic will make deep primary reference for this study. This new research presses low voltage features to circuit stated. By using profoundest results of the study, we will develop FFT processor designs as an example of digital wireless circuits. The FFT processor can operate...
Performance and power are the first order design metrics for network-on-chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for multicores/CMPs. However, NoCs can be plagued by higher power consumption and degraded throughput if the network and router are not designed properly. Towards this end, this paper proposes a novel router architecture, where we...
Customizing the instruction set for particular applications has become a successful practice in the industry in the design of application specific processors. Following the same principle, this paper evaluates the impact of embedding specialized instructions within the processing elements (PEs) of coarse grained reconfigurable arrays (CGRAs). We systematically extract and select regular clusters of...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
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