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Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
The interest in non-synchronous design of digital circuits is growing due to technology scaling into deep submicron transistor geometries and to the problems this scaling causes to keep synchronous design advantageous. To enable most non-synchronous styles, the C-element is a fundamental device that has to be available as logic primitive. A recently proposed design flow improved a standard cell library,...
An ultra-low voltage performance of nanowire-transistors-based CMOS circuits is investigated using the Spice model parameters. All Spice model parameters of BSIM4 are extracted from measurement data of nanowire transistors fabricated on 300 mm SOI wafer. The delay time and the power consumption of NW-Tr.-based and bulk-Tr.-based CMOS circuits are examined. The operation voltage of NW-Tr.-based inverter...
Packet scheduling algorithms are viewed as one of the key mechanisms for increasing the diversity order, robustness and effectiveness of a wireless multi-user communication systems. Traditional packet scheduling algorithms are designed to save energy at the Base-station(BS) in downlink by exploiting tradeoffs between spectral efficiency, delay and energy while at the same time meeting the QoS requirements...
Cryptographic devices can be subject to side-channel attacks. Among those attacks, Differential Power Analysis (DPA) has proven to be very effective and easy to perform. Several countermeasures have been proposed in the literature. However, the effectiveness of these counter measures is still evaluated by resort-ing to intensive DPA simulations and constitutes a very time-consuming design task. In...
The design mainly discussed the low power consumption cymometer's circuit implementation plan. It is based on the most practical digital system simulation VHDL language. Then through compilation, simulation, downloaded to the FPGA device up with MAX+PLUS software, investigated cymometer's practicable. And through the use of electronic circuit simulation EWB software verified cymometer's correct in...
In this paper the graph energy and electrical power consumption of various parallel prefix adders (PPA) are measured and investigated. By comparison the graph energy of PPAs with their power consumption, a linear relation between them is considered. Moreover, the measurements represent direct relation between arcs number and graph energy in PPA structures. Using these results a new PPA (proposed I)...
With the ever increasing needs of power aware architecture and circuit design in recent years, how to reduce the power consumption of processors without sacrificing performance has become an important issue. In this paper, we propose a new method for low power branch prediction-Hedging Filter, which combines filtering scheme reducing dynamic power consumption with hedging prediction mechanism lowering...
Scan shift power can be reduced by activating only a subset of scan cells in each shift cycle. In contrast to shift power reduction, the use of only a subset of scan cells to capture responses in a cycle may cause capture violations, thereby leading to fault coverage loss. In order to restore the original fault coverage, new test patterns must be generated, leading to higher test-data volume. In this...
Test technologies for integrated circuits have traditionally tried to maximise test data compression rates, because these are essential for keeping test time and costs low. However, power consumption during the test process is a problem that has been addressed on recently. Excessive power consumption may result in thermal stress and increased voltage drops within the circuit, which implies increasing...
This paper presents a new dynamic circuit design style based on the differential cascade voltage swing logic. The design style is proposed as a data driven dynamic differential logic design style. The proposed design style offers significant performance advantages over conventional DCVSL and Differential Domino with reduced power consumption. The pre-charge and evaluation phases are controlled by...
Wordlength determination is a crucial task in digital hardware implementations for green computing because the wordlength affects power consumption and system performance. Digital hardware requires careful wordlength design for a sufficient dynamic range. Nevertheless, wordlength can be reduced during better conditions. We present a modeling approach for dynamic variable wordlength (DVW) in digital...
Worst-case design uses extreme process corner conditions which rarely occur. This costs additional power due to area over-dimensioning during synthesis. We present a new design strategy for digital CMOS IP that makes use of forward body biasing. Our approach renders consistently a better performance-per-area ratio by constraining circuit over-dimensioning without sacrificing circuit performance. Dynamic...
This paper describes the low-power design of a MOS current-mode logarithmic adder. The adder utilizes the Brent-Kung tree structure. The design strategy adopted is very simple and effective. Moreover, it can be utilized also for other types of logarithmic adders. To validate it, several adders were designed in a TSMC CMOS 130 nm technology. Results of simulations indicate that the proposed methodology...
The use of multiple voltage domains in an integrated circuit has been widely utilized with the aim of finding a tradeoff between power saving and performance. Level shifters allow for effective interfacing between voltage domains supplied by different voltage levels. In this paper we present a low power level shifters in the 90 nm technology node capable of converting subthreshold voltage signals...
Static random access memories (SRAMs) comprise an increasingly large portion of modern very large scale integrated (VLSI) circuits. The increasing importance of embedded SRAM is due to its low circuit activity factor, leading to low active power density, and productivity of design. The power consumption has become an important issue and has lead to the development of numerous schemes aimed at limiting...
Due to the importance of power/ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the power/ground network is designed...
Optimization of power and delay is very important issue in low-voltage and low-power applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors and low-threshold to some others. Here, the polarity of the MOSFETs is considered as the selection criteria for assigning threshold. In order to achieve the best leakage...
This paper presents a high performance 16times16 bit 2's complement multiplier using MOS current mode logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mum CMOS...
Subthreshold region of operation has gained wide research interest for applications requiring Ultra low power consumption and medium frequency of operation. Double gate MOSFETs are proved to be better candidates for subthreshold operation due to their near ideal subthreshold slope and negligible gate capacitance. However it is not yet clear whether symmetric (SDG) or Asymmetric (ADG) DG with options...
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