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In this paper, Low Voltage CMOS Timing Generator Using Array of Digital Delay Lock Loops is presented. The timing generator is implemented as an array of Delay Locked Loops, providing wide operating frequency range. This architecture enables a timing generator with sub-gate delay resolution to be implemented. The proposed Delay Lock Loops use a Dual Phase and Frequency Detector along with a charge...
A novel parallel semi-systolic semi-scanned array architecture is proposed for the implementation of four-dimensional (4-D) IIR filters. These filters have emerging applications in computed tomography (CT), volumetric ultrasound, and light field processing for computer vision. The proposed architecture can be applied to a broad class of 4-D IIR filters, and we show results for a frequency-planar depth-selective...
A design, implementation and evaluation of low power accelerator CMA-2 were introduced. Evaluation result with real chip shows that the maximum energy efficiency is 233.7 MOPS/mW.
A fully-integrated 8-antenna array transmitter in 65-nm CMOS for short range and portable millimeter-wave (mm-wave) active imaging applications is presented. Each of 8 resistor-less pulse generators (PG) are connected to an on-chip dipole-patch antenna and to a 7-bit digitally programmable delay circuit (DPDC). A 20-bit on-chip jitter and relative skew measuring circuit is also implemented to dynamically...
A highly energy efficient reconfigurable accelerator called CMA (Cool Mega-Array) is proposed. It consists of a large Processing Element (PE) array without memory elements for maintain result of ALU and configuration data, a small simple programmable micro controller for data management, and the data memory. Unlike traditional coarse grained reconfigurable processors, the power consumption for hardware...
A coarse grained dynamically reconfigurable processor (CGDRP) with both Dual Vdd and Dual Vth is proposed with power centric Dual Vdd and Dual Vth assignment policies. The evaluation result shows that the Vth and Vdd assignment optimization algorithm reduces 37% of total consuming power within keeping the operational frequency.
In here we consider the problem of automatic synthesizing, from C to Verilog, circuits that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules, buffers/queues or multi-port memories. Typically highlevel synthesis compilers assume fixed and known memory latencies thus the technique presented...
This paper presents a new processor array architecture for scalable radix 8 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architectures extracted by G. Todorov. Moreover, the multiplier bits are fed serially to the first processing...
SLD(Silent Large Datapath)-1 is a prototype accelerator for media processing consisting of a large Processing Element (PE) array which includes 24bit 8 × 8 PEs with combinatorial circuits and a small micro-controller for data memory access. It was fabricated in 2.1mm × 4.2mm 65 nm CMOS, and achieves 1.356GOPS/11mW sustained performance by reducing overhead of clock tree and the benefit of voltage...
A simple array-based test structure has been developed to characterize AC variability in deeply scaled MOSFETs. Each test structure consists of 128 devices under test (DUTs) whose relative delays are characterized using a logic gate-based delay detector circuit. The delay measurement technique only requires a single off-chip DC voltage measurement for each DUT. A design-time optimization is performed...
AMD's 2-core "Bulldozer" module contains 213 million transistors in an 11 metal layer 32nm HKMG SOI CMOS process and is designed to operate from 0.8 to 1.3V. This new micro-architecture improves performance and frequency while reducing area and power compared to a previous AMD x86-64 CPU in the same process. To achieve these goals, the design reduced the number of F04 inverter delays/cycle...
SAT-based BMC is promising for directed test generation since it can locate the reason of an error within a small bound. However, due to the state space explosion problem, BMC cannot handle complex designs and properties. Although various optimization methods are proposed to address a single complex property, the test generation process cannot be fully automated. This paper presents an efficient automated...
To resolve the latency problem of implementing Montgomery modular multiplication algorithm using the linear systolic array, this paper proposes the improved Montgomery algorithm, and improves the systolic array by combining the long carry save adder (CSA) structure. This paper also proposes a series of methods to optimize the critical path and a non-waiting modular multiplication strategy which can...
Two-dimensional (2D) beam filters find applications in highly-selective directional enhancement of spatio-temporal (ST) plane-waves (PWs). A 2D raster-scanned (RS) wave-digital filter (WDF) hardware architecture, using a uniform linear array (ULA) of sensors, based on a 2D LR-ladder prototype network is proposed for obtaining M independently-steerable broadband beams having adjustable selectivity...
Multi-core processing is a growing industry trend as single core processors rapidly reach the physical limits of possible complexity and speed. In case of single core processors, the increased performance incurs the more heating and cooling arrangements, as heating is a consequence of power dissipation. The cache design in existing SMT and superscalar processors is optimized for latency, but not for...
A system is composed of 64 channels of analog front-end pulser/receiver, 64 channels of Time-Gain Compensation (TGC), 64 channels of high-speed digitizer, and DSP-based beamformer implementation. The data are transferred to a PC via an Ethernet card. The system provides 64 channels of excitation pulsers while receiving simultaneously at a 120–200 MHz sampling rate at 12-bit resolution. The digitized...
Phase quantization error is defined as the difference in the ideal and discretized inter element phase delays and is dependent upon the delay resolution of the ultrasound imaging system. Large quantization error values can create phasing lobes which cause beam anomalies and may degrade image quality. Described is a method which uses Phase Locked Loop (PLL) components embedded within standard Field...
Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz...
This paper explores the design of parallel multipliers for Quantum-Dot Cellular Automata. Array multipliers, Wallace multipliers, Dadda multipliers, and quasi-modular multipliers are designed and analyzed. Quasi-modular multipliers use 4 (n/2 × n/2) modules to make n × n multipliers are also considered. All of these designs are constructed using coplanar layouts. The delay, area and complexity are...
Quantum-dot Cellular Automata (QCA) technology is a promising alternative to CMOS technology. It is attractive due to its fast speed, small area and low power consumption. To explore the characteristics of QCA technology, digital circuit design approaches have been investigated. Due to the inherent wire delay in this technology, QCA appears to be suitable for pipelined architectures particularly....
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