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Efficient detection and reliable matching of image features constitute a fundamental task in computer vision. When real-time operation is required, the solution to this problem becomes a real challenge, because of increased processing requirements. Scale Invariant Feature Transform (SIFT) is considered as a stable and robust algorithm for the extraction of invariant features, however special hardware...
TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode front-end ASIC developed to readout the new inner tracking detector of the BESIII experiment, carried out at BEPCII in Beijing. The detector is planned to be installed during the 2018 upgrade and features an innovative three-layer triple-CGEM (Cylindrical Gas Electron Multiplier) with analog readout. The ASIC comprises 64 channels,...
RANSAC is a popular and robust fitting algorithm. In the field of image processing, RANSAC can be successfully used to reject false correspondences between similar images. Due to its iterative nature, RANSAC is computationally demanding and time consuming. When the target application operates in real-time, conventional approaches based on personal computers usually fail to meet the requirements. In...
The ATLAS experiment will follow the upgrade steps of the Large Hadron Collider (LHC), which will undergo a series of upgrades to increase the luminosity in the next ten years. During the Phase-I upgrade, a new component will be designed for the ATLAS Level-1 calorimeter trigger system to maintain the trigger acceptance against the increasing luminosity — the global feature extractor (gFEX). The gFEX...
The analysis of the electrocardiogram (ECG) signal is used extensively in the diagnosis of different heart diseases. One of the major tasks to be provided is the accurate determination of the QRS complex. Due to its characteristic shape QRS detection in an ECG signal is necessary for efficient extraction of beat-to-beat intervals (RR). In this paper, a simple and reliable Field Programmable Gate Array...
Keystroke dynamic is one of the behavioral biometric identification techniques which distinguish users through their unique typing style. This paper presents two techniques to measure the distance metric between two samples of the same user. Two methods are used to implement the normalized distance between two samples of the same user; first method uses JavaScript for measuring the feature extraction...
This paper presents an efficient FPGA design that can classify 48 different traffic signs at real-time. The method is based on histogram of oriented gradients (HOG) feature extraction and support vector machine (SVM) for classification. A full-pipeline, resource efficient architecture is presented with detail design of each block. The FPGA implementation has a system clock of 241.7 MHz with an absolute...
Drivers' failure to observe traffic signs, especially the stop signs, has led to many serious traffic accidents. Video-based traffic sign detection is an important component of driver-assistance systems. In earlier systems, simple color and shape-based detection methods have been broadly applied. Recently, feature-based traffic sign detection algorithms are proposed to obtain more accurate results,...
Local Binary Pattern (LBP) is texture operator used in preprocessing for object detection, tracking, face recognition and fingerprint matching. Many of these applications are performed on embedded devices, which poses limitations on the implementation complexity and power consumption. As LBP features are computed pixelwise, high performance is required for real time extraction of LBP features from...
In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves...
This paper presents the implementation of a low-power and implantable neuroprocessor on low-cost nano-FPGA for data reduction and on-the-fly spike sorting in Brain Machine Interface applications. Detailed analysis of efficient utilization of the hardware resources, power consumption and design scalability are provided. The prototype we report here enables simultaneous processing of 32-channel data...
Statistical texture features extraction algorithms can be classified into first, second, and higher order. The difference between these classes is that the first-order statistics estimate properties of individual image pixel values, while in the second and higher order statistics estimate properties of two or more image pixel values occurring at specific locations relative to each other. The most...
Specific architectures for different low level vision modalities have been developed and described using reconfigurable hardware. Each of them tries to solve a single low level vision problem: optical flow, disparity, segmentation, tracking, etc. We introduce a novel architecture that includes multiple processing engines in a massively parallel low level vision processing engine of very high complexity...
The paper introduces a hardware design method machine vision based of textile defect detection system. The system can effectively replace manual monitoring of textile production lines, which has greatly improved the production efficiency and automation. The system uses Samsung's ARM7 chip S3C44B0 as the production's core processor, using the FIFO memory to realize data cache of OV7620 image sensor,...
In this study, an FPGA based method has been presented for detection of broken rotor bar faults occurred in induction motors. The proposed method takes one phase current signal and extracts feature signal by applying Hilbert transform. Each state of finite state machine is obtained calculating the entropy value on feature signal. The state transition matrix is constructed in real time on FPGA environment...
SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation...
SIFT is regarded as one of the most robust feature point detection algorithms in CV field. The feature point detection part, allocating final positions of all feature points, majorly defines the accuracy and stability of the whole system. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing dual-pixel processing and the 3-stage-interpolation pipelined...
In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms...
We present in this work an image component labeller-and feature extraction module that can operate in real-time. This labeller is suitable for smart cameras and Field Programmable Gate Arrays (FPGA). We show in our work how complex gray value features of image components can be calculated in parallel with label assignment without first resolving complex chains of merged labels. The labeller and a...
Window operations which are computationally intensive and data intensive are frequently used in image compression, pattern recognition and digital signal processing. Reconfigurable hardware boards provide a convenient and flexible solution to speed up these algorithms. This paper studies the effect of loop unrolling on the area, clock speed and throughput based on a data schedule method to find the...
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