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Protecting control planes in networking hardware from high rate packets is a critical issue for networks under operation. One common approach for conventional networking hardware is to offload expensive functions onto hard-wired offload engines as ASICs. OpenFlow networks are expected to provide greater network control flexibility by an open interface to the packet-forwarding plane and by centralized...
Software Defined Networking (SDN) offers traffic characterization and resource allocation policies to change dynamically, while avoiding the obsolescence of specialized forwarding equipment. Open Flow, a SDN standard, is currently the only standard that explicitly focuses on multi-vendor openness. Unfortunately, it only provides for traffic engineering on an integrated basis for L2-L4. The obvious...
This paper describes EXECO, a library that provides easy and efficient control of local or remote, standalone or parallel, processes execution, as well as tools designed for scripting distributed computing experiments on any computing platform. After discussing the EXECO internals, we illustrate its interest by presenting two experiments dealing with virtualization technologies on the Grid'5000 testbed.
This paper presents a baseband processor developed for SDR that supports such wireless modes as WLAN, WiMAX, W-CDMA, and LTE. To achieve both the high area-efficiency of dedicated hardware and the high flexibility of DSP, we have developed a hetero-multi-processor architecture that maps each processing task either to a newly developed stream-access-oriented processor or to a parameterized hardware...
This paper presents a scalable host controller for modular hardware accelerator. Designing a hardware method of scalable host controller can handle multiple processing units at the same time. Currently in System on Chip (SoC) design, multiple processing units accessing the memory to request a task lead to inefficient communications due to bus congestion. In addition, designing a scalable host controller...
A parallel unified processor for graphics and vision is developed. It achieves 371.9G0PS/W in full operation through a 6-way VLIW datapath, reconfigurable processing elements for graphics and vision mode, and a pixel arranger for data-level parallelism. The pose-estimation engine achieves 0.89 μW/fps for marker-based augmented reality.
Network processors (NPs) promise a flexible, programmable packet processing infrastructure for network systems. To make full use of the capabilities of network processors, it is imperative to provide the ability to dynamically adapt to changing traffic patterns and to provide run-time support in the form of a network processor operating system. The differences to existing operating systems and the...
A method for control employing rule-based search is reviewed, and a Rule-Based Controller achieving economical real-time performance is described. Code optimization, in the form of LISP-to-Pascal knowledge base translation, provides real-time search execution speed and a processing environment enabling highly integrated symbolic and numeric computation. With a multiprocessor software architecture...
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