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The HEVC standard is one of the newest video coding standards developed to face the upcoming challenges concerning video processing. HEVC allows only one type of entropy encoder, which is the CABAC (Context Adaptive Binary Arithmetic Coding), responsible for the symbolic data representation in order to translate the final video bitstream to a smaller number of bits. This work presents hardware architecture...
The HEVC is one of the most recent video coding standards, developed in order to face upcoming challenges, due to higher video quality and resolution. One of the HEVC components is the entropy encoder, which consists only of the Context Adaptive Binary Arithmetic Coding (CABAC) algorithm. The CABAC algorithm imposes some severe difficulties in order to achieve increasing throughput, due to the high...
The demand for higher quality video has increased in the past few years, due to the huge amount of electronic devices that process digital video in even higher resolutions. For that purpose, video coding techniques are used, which have, as main goal, the reduction of the required representation to process a digital video. Furthermore, embedded hardware video solutions are sought for both industry...
The calculation of the Sum of Absolute Differences (SAD) is one of the most time-consuming operations of the video encoder compatible with the new High Efficiency Video Coding (HEVC) standard. SAD hardware architecture employs an adder tree to accumulate the coefficients from absolute difference between two video blocks. This paper proposes the exploration of the different adder compressors structures...
In this paper, we design new efficient VLSI architecture for Integer Discrete Cosine Transform (DCT) included in the last new High Efficiency Video Coding (HEVC) standard. The proposed architecture has 4×4/8×8/16×16/32×32 Transform Units (TUs) operating in a parallel way to calculate two dimensional (2D) integer DCT using one block 1-D DCT and one transpose memory. Transform 1D is first calculated...
This work presents a comparison of two implementations of the last software version of The High Efficiency Video Coding (HEVC) decoder in a single low cost processor ARM Cortex-A series using NEON architecture which is a Single Input Multiple Data (SIMD). By using this technology of optimization, the whole execution time is reduced up to x4. We have analyzed separately all the blocks in the decoder...
High Efficiency Video Coding is the latest video standard aiming to replace H264/AVC standard by improving significantly the coding efficiency and the compression performance which allows HEVC to be mostly suitable for high-definition videos for multimedia applications. However, the encoding process requires a high computational complexity that needs to be alleviated. Hence, the paper proposes a software...
HEVC is the newest standard developed by the Joint Collaborative Team on Video Coding (JCT-VC). HEVC or H.265 includes several modifications compared with its predecessor the H.264/AVC, especially those involved in Fractional Motion Estimation (FME). This work is focused on the FME process that is an important part of an HEVC CODEC, because of its high computational complexity that demands a 40–60%...
Sample Adaptive Offset (SAO) is a new tool added in latest video coding standard (HEVC) to achieve better coding efficiency resulting in higher visual quality. In this paper, we propose efficient and high performance VLSI architecture as well as data transfer scheme for SAO decoder that can work in a pipelined manner achieving 4K (Ultra-HD) resolution at 60 fps in video codec engine. The proposed...
This paper presents an efficient hardware design for the Discrete Cosine Transform (DCT) of High Efficiency Video Coding standard (HEVC). This hardware supports all HEVC transform sizes: 4×4, 8×8, 16×16, and 32×32 including any combination of the Transform Unit (TU) sizes. The proposed DCT architecture has a constant throughput of 32 coefficients per cycle, independently of the transform sizes combination...
Recently, HEVC standard have been proposed as a solution for transmitting high quality videos with half bit rate compared to the previous H.264 standard. One of the main properties of the new standard is the variety of the transform unit sizes. In this paper, we propose a new reconfigurable pipelined architecture for Inverse Discrete Cosine transform, which is used in both the HEVC encoder and decoder...
In order to enable a system which offers compatibility with currently existing H.264/AVC based systems, 3D functionality, and a low overall bitrate, a multiview H.264/HEVC hybrid architecture was proposed in the context of 3D applications and standardization. This paper presents an algorithm to reduce the complexity of this multiview hybrid architecture by reducing the encoding complexity of the HEVC...
This paper presents a highly parallel motion estimation architecture for High Efficiency Video Coding (HEVC) encoder. The proposed architecture has 16 processing units operating in parallel to calculate the sum of absolute difference values of all possible variable prediction block sizes. Hence, it calculates the bit cost regarding every partition in order to find the best matching candidate in terms...
A novel hardware accelerator for the High Efficiency Video Coding (HEVC) intra prediction is presented in this paper in order to reduce the computation complexity within this standard and to accelerate the concerned calculations. We propose a new pipelined structure that we called Processing Element (PE) to execute all angular modes, and we repeat it in five paths that our architecture composed of...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
Transformation and quantization in block based video codecs introduces blocking artifacts at edges. Special optimized video filter called de-blocking filter is applied on 4×4/8×8 block boundary to enhance visual quality and improve prediction efficiency. Most of the recent video codecs, H.264, H.265 (HEVC), VC-1 uses in-loop de-blocking (LPF) filter in decoder path. Each video codec standard defines...
This paper presents design and implementation of a high throughput interpolator for the fractional motion estimation in HEVC systems. Novel data reusing scheme and highly parallel architecture are proposed such that timing efficiency and thus processing throughput of the system are enhanced. The detailed circuit architecture and timing analysis for the proposed interpolator will be given. Moreover,...
In this paper, we propose an optimized hardware architecture for the implementation of intra prediction in High Efficiency Video Coding standard (HEVC) decoder developed by the Joint Collaborative Team on Video Coding (JCT-VC) which is the common group released by the ITU-T Video Coding Experts Group and the ISO/IEC Moving Picture Experts Group. HEVC is designed to achieve better coding efficiency...
In this paper, a stochastic computation (SC) based hardware implementation for 4-point DCT in the emerging High Efficiency Video Coding (HEVC) standard was provided. HEVC employs integer DCT with larger transform coefficients than the preceding standards. Hence the multipliers and adders therein are also more hardware consuming. With SC theory applied to DCT hardware design, the circuit implementation...
High Efficiency Video Coding (HEVC) is new video coding standard beyond H.264/AVC. In this paper, an area and throughput efficient 2-D IDCT/IDST VLSI architecture for HEVC standard is presented. Adopting proposed data flow scheduling and shared constant multiplication structure, the architecture supports variable block size IDCT from 4×4 to 32×32 pixels as well as 4×4 pels IDST. Using 65nm technology,...
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