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Smart City is becoming a commonly-used term to describe the concept of utilizing information and communication technologies (ICT) to enhance urban services and improve the quality of life for citizens. All communications should be fast and properly protected against unauthorized eavesdropping, interception, and modification. Therefore high speed and strong cryptography is required. Advanced Encryption...
Deoxyribonucleic Acid (DNA) sequence alignment is essentially a way of comparing two or more DNA sequences with aim to find regions of similarities among them. The Smith-Waterman (SW) algorithm is a local alignment algorithm which is able to identify mutation in DNA sequences. However, the aforementioned algorithm tends to be slower in computation of long DNA sequences. Over decades ago, Field Programmable...
Image scaling is a fundamental algorithm used in a large range of digital image applications. In this paper, we propose an efficient VLSI architecture for a novel edge-directed linear interpolation algorithm. Our VLSI design is implemented using high level synthesis (HLS) tool, which generates RTL modules from C/C++ functions. HLS provides significantly improved design productivity compared to the...
This paper presents the outer-round only pipelined architecture for a FPGA implementation of the AES-128 encryption processor. The proposed design uses the Block RAM storing the S-box values and exploits two kinds of Block RAM. By combining the operations in a single round, we can reduce the critical delay. Therefore, our design can achieve a throughput of 34.7 Gbps at 271.15 Mhz and 2389 CLB Slices...
The FPGA-based high throughput 128 bits AES cipher processor is proposed in this paper. We present an equivalent pipelined AES architecture working on CTR mode to provide the highest throughput up to date through inserting some registers in appropriate points making the delay shortest, when implementing the byte transformation in one clock period. The equivalent pipelined architecture does not change...
This paper shows the algorithm implementation for a field-programmable gate array (FPGA)-based design for people counting using a low-level head-detection method. The hardware (HW) implementation on an FPGA allows the capture and online processing in real time on the same chip. Different annular patterns are used to process in parallel the image and detect heads of different sizes. Preprocessing and...
In this work, we present architecture for real-time implementation of INTRA 4 times 4 algorithm used in H.264/AVC baseline profile video coding standard. The INTRA 4 times 4 is composed by intra prediction 4 times 4, integer transform 4 times 4, quantization 4 times 4, inverse integer transform 4 times 4, inverse quantization 4 times 4. This hardware is designed to be used as part of a complete H...
Recursion is a powerful technique used to solve problems with repeating patterns, and is a fundamental structure in software. To date there is no known general way to apply a recursive solution to reconfigurable hardware; it is considered difficult to implement, of low performance and resource-intensive. In this paper we extend previous results on hardware structures for recursion by V. Sklyarov,...
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