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Although standard 32/64-bit arithmetic is sufficient to solve most of the scientific-computing problems, there are still problems that require higher numerical precision. Multiple-precision arithmetic (MPA) libraries are software tools for emulation of computations in a user-defined precision. However, availability of a reconfigurable cards based on field-programmable gate arrays (FPGAs) in computing...
The template matching is an important technique used in pattern recognition. It aims at finding a given pattern within a frame sequence. Pearson's Correlation Coefficient (PCC) is widely used to evaluate the similarity of two images. This coefficient is computed for each image pixel, which entails a computationally very expensive process. This paper proposes an implementation of the template matching...
This paper presents novel techniques of using hybrid prototyping for early power-performance analysis of MPSoC designs with multiple clock domains. The fundamental idea of hybrid prototyping is to simulate a design with multiple cores by creating an emulation kernel in software on top of a single physical instance of the core. However, so far hybrid prototyping has been limited to homogeneous multicores...
We present an efficient hardware implementation of a quasigroup block cipher system. Power and resource comparisons are done with AES and we show that the proposed quasigroup system provides an inexpensive alternative for SCADA networks and other low powered, resource constrained devices.
The efficient use of embedded systems relies heavily on appropriate strategies to optimize the execution time and power consumption. These systems are characterized by resource restrictions, including the amount of memory available for applications. However, there are several techniques that make the embedded systems more efficient. One of those techniques is the code compression; the proposals found...
Fast and efficient accumulation arithmetic circuits are critical for a broad range of scientific and embedded system applications. High throughput accumulation circuits are typically hand designed for specific vector lengths requiring the circuit to be modified when the lengths are changed. In this work we present a new design approach that can achieve low latency and near optimal throughput for input...
Artificial Neural Networks (ANN) are used to perform tasks like classification, pattern recognition and function approximations in many cases to which traditional approaches are not well suited. Hardware implementations have been presented, mainly in academical works, in order to take advantage of the inherent parallelism in ANNs. In the field of embedded systems it is desirable to have faster and...
Using IEEE 1588 for highly accurate clock synchronization between nodes of a distributed system has become a widely accepted approach. IEEE 802.3/Ethernet is frequently utilized as communication layer to exchange the Precision Time Protocol (PTP) messages specified in the IEEE 1588 standard. 10/100/1000 MBit Ethernet communication is commonly used by now. In contrast, fiber optics based 10 GBit Ethernet...
Chaotic encryption schemes are believed to provide a greater level of security than conventional ciphers. In this paper, a chaotic stream cipher is first constructed and then its hardware implementation details using FPGA technology are provided. Logistic map is the simplest chaotic system and has a high potential to be used to design a stream cipher for real-time embedded systems. The cipher uses...
This Traditional UART IP hard core is poor at flexibility and transportability while UART IP soft core is only based on poll and interrupt mode at present which consumes so much time of CPU that the performance of embedded system is reduced greatly. UART IP soft core based on DMA mode is proposed and well elaborated using the characteristic of DMA. The IP core is AVALON bus-compatible with the control...
This paper presents the results of the dependability validation of a cryptoprocessor to SEU effects. The dependability validation was carried out running a testbench, initially using functional simulation, and later using in-system hardware execution. For the fault injection, a modified memory cell and a strategy of pseudorandom generation of states into FSMs are proposed. The testbench was simulated...
FPGAs, (Field-Programmable Gate Arrays) are often used for embedded image processing applications. Parallelism, and in particular pipelining, is the most suitable architecture for supporting the required high throughput. Although pipelining is a well known technique for hardware design and is simple to describe, our experience has been that people have many problems implementing working pipelines,...
Due to the runtime flexibility offered by field programmable gate arrays (FPGAs), FPGAs are popular devices for stream processing systems, since many stream processing applications require runtime adaptability (i.e. throughput, data transformations, etc.). FPGAs can offer this adaptability through runtime assembly of stream processing systems that are decomposed into hardware modules. Runtime hardware...
Advances in portable devices and location-aware applications have necessitated the research in sophisticated yet small-footprint hardware and software in embedded systems, while the proliferation of the Web and distributed database systems has led to new data mining applications. We are investigating the utilization of reconfigurable hardware, due to its flexibility and performance, for data mining...
Sorting is an important operation for many embedded computing systems. Since sorting large datasets may slowdown the overall execution, schemes to speedup sorting operations are needed. Bearing in mind the hardware acceleration of sorting, we show in this paper an analysis and comparison among three hardware sorting units: sorting network, insertion sorting, and FIFO-based merge sorting. We focus...
This paper presents the first implementation of built-in self-test (BIST) of field programmable gate arrays (FPGAs) using a soft core embedded processor for reconfiguration of the FPGA resources under test, control of BIST execution, retrieval of BIST results, and fault diagnosis. The approach was implemented in Xilinx Virtex-5 FPGAs but is applicable to any FPGA that contains an internal configuration...
This work presents an architecture to compute matrix inversions in a reconfigurable digital system, benefiting from embedded processing elements present in FPGAs, and using double precision floating point representation. The main module of this system is the processing component for the Gauss-Jordan elimination. This component consists of other smaller arithmetic units, organized in pipeline. These...
Commercial soft processors are unable to effectively exploit the data parallelism present in many embedded systems workloads, requiring FPGA designers to exploit it (laboriously) with manual hardware design. Recent research has demonstrated that soft processors augmented with support for vector instructions provide significant improvements in performance and scalability for data parallel workloads...
In many embedded systems for video surveillance distinctive features are used for the detection of objects. In this contribution a real-time FPGA implementation of a feature detector, namely the SUSAN algorithm is described. As the original SUSAN algorithm performs poorly on non-synthetic images a significant quality improvement of this algorithm is presented. The hardware accelerator outperforms...
Todaypsilas systems are more complex and need higher performance. To accomplish this, systems include more hardware compared to software. This increases the use of FPGAs in modern systems because of its reconfiguration capabilities. FPGA contains many hardware components, which are utilized to perform operations directly in hardware. There are two problems related to this issue, first is high performance...
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