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With in the process temperature limit of less than 400 °C for via last technology, a simple method to improve the barrier ability of Ti layer in through Si via (TSV) has been studied. After annealing the TSV structures in vacuum at temperatures up to 400 °C, we did observe a tremendous improvement in leak current characteristics for SiO2 dielectric. It was found that the self-formed TiSix at the interface...
Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal...
Chemical Mechanical Polishing (CMP) on thinned bonded wafer is one of the key challenges in the entire via-last TSV process flow. This paper addresses the issue of oxide loss and barrier metal residue during CMP process. The impact of pre-CMP thermal budget on (i) CMP polishing rate, (ii) uniformity and (iii) selectivity to the underlying dielectric on bonded wafers is investigated. We further looked...
Silicon interposers enable advanced package architectures through the integration of multiple die and passive components onto a single silicon substrate, while offering high interconnect density and low thermal expansion mismatch. This paper will describe the processing and characterization of copper-filled through silicon vias (TSVs) for Si interposers and related three-dimensional wafer-level packaging...
High density 3D-LSI with W-TSV for signal line and Cu-TSV for power/GND line, and Cu-TSV containing W stress absorbing layers were investigated for the induced thermo-mechanical stress in 3D-LSI Si die/wafer after wafer thinning and bonding using micro-Raman spectroscopic technique. Stress mapping analysis revealed that W-TSV has induced less thermo-mechanical stress in LSI Si, whereas the Cu-TSV...
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