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Combining the self-compensated topology with the negative-impedance-compensation technique, a differential TIA with enlarged input-capacitance tolerances is designed in a 0.18μm CMOS technology. The DR is measured to be >20dB without using any gain control. The complete TIA IC consumes 40mW from a 1.8V supply.
A new RF model for an AMOS varactor is presented for 0.18mum CMOS. This model is the first reported for frequencies above 20 GHz in a standard CMOS technology. It does not rely on boundary conditions for different modes of operation and all component values in the model are calculated using clearly defined physical equations, making it easily adaptable to any varactor layout or even other CMOS technology...
This paper examines the design of a 10 Gbps transimpedance amplifier (TIA) in 0.18 mum CMOS technology. In order to compensate for the high parasitic capacitances in the CMOS process, this design uses a shunt and series inductive peaking technique to achieve the required transimpedance bandwidth. A noise analysis on the input stage of the TIA is shown. This noise model is used to determine the optimum...
In this paper we present an ultra-low voltage gate-input operational transconductance amplifier using pMOS input devices and nMOS load devices with local common-mode feedback. This topology has a good intrinsic common-mode rejection. Simulations for a two-stage, 0.5 V fully differential operational transconductance amplifier (OTA) with a gain of 55 dB and a common-mode rejection ratio of 61 dB are...
A wideband differential transimpedance amplifier of an optical receiver is realized in a 0.18mum standard CMOS technology for the applications of Gigabit Ethernet data communication. The amplifier incorporates the regulated cascode (RGC) configuration to achieve strong immunity to large input parasitic capacitance and also exploits shunt inductive peaking technique to extend the bandwidth. Consequently,...
A monolithically integrated optical receiver with spatially modulated light (SML) detector in an unmodified 0.18 mum CMOS technology is presented. The SML-detector exhibits high bandwidth by canceling out the diffusion component and suppressing the slow diffusion tail effect. The receiver comprises a zero-pole cancellation configuration preamplifier stage and a differential amplifier stage. With behavior...
A fully differential low noise amplifier with a special care for mixer input stage is presented. It considers mixer input stage to comply with DC bias condition of low noise amplifier output without bias tee using a common-mode feedback circuitry (CMFB). The proposed fully differential low noise amplifier is focused on the 915MHz an unlicensed frequency ISM band communication. This low noise amplifier...
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