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Conductance variations in nanoelectronic resistive switches seriously affect the performance of hybrid CMOS/memristive circuits. In order to capture cycle-to-cycle variability by circuit simulation a standard model was extended for resistive switches based on the electrochemical metallization effect. The extension incorporates an additional process that simulates the randomness of the filament growth...
This paper proposes a fast, precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool (MATLAB/Simulink) without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the formula based on the circuit operation and by applying...
This paper presents a new method to recover energy in an Analog-to-Digital Converter (ADC) based on the principle of adiabatic charging. The ADC comprises an Adiabatic Charging Charge Redistribution (ACCR) DAC, a dynamic comparator, and a Successive-Approximation-Register (SAR) counter. Charges in the ACCR DAC can be recovered through a resonant power supply and adiabatic switch. These charges can...
The design plan and HSPICE measurement of a high acquisition speed for a sample of 8-bit CMOS differential successive approximation register (SAR) Analog-to-digital converter (ADC) are presented. The operation of the conventional main switch-capacitor array is divided into two switch-capacitor arrays. Such that, one switched-capacitor array is used to define the four most-significant bits, while the...
As CMOS technology continues to scale, the accurate prediction of silicon timing through the use of pre-silicon modeling and analysis has become especially difficult. These timing mismatches are important because they make it hard to accurately design circuits that meet timing specifications at first-silicon. Among all the parameters leading to the timing discrepancy between simulation and silicon,...
A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 ??m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation...
In this paper, a modified auto zeroed integrator is used to design and simulate a low-voltage high-speed and accurate switched capacitor pseudo 2-path filter. The filter is a sixth-order Chebyshev band-pass filter operating at sampling frequency of 1MHz and center frequency of 250 kHz with a quality factor of 50. The circuit is simulated using HSPICE and 0.25??m CMOS technology.
Much attention has been paid to dynamic circuit in current low power design. Since the BiCMOS circuit has advantages of both the CMOS circuit and the TTL circuit, it has gained more and more application. In this paper, a new structure and the design method at switch level of the binary dynamic BiCMOS circuit has been proposed based on an n-type BiCMOS dynamic circuit. The circuits designed following...
A current-based close loop track-and-hold circuit with a speed of 50 MS/s and 8-bit resolution for plusmn0.8 V input range is implemented using a voltage-control current source and a current switch. The proposed circuit has the advantage of high input impedance and stable output. SPICE simulation using 0.35 mum SMIC CMOS technology with plusmn1.65 V supply showed that the proposed track-and-hold circuit...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper describes a design flow for the circuit-level optimization of a technology. The concurrent exploration of device characteristics and library design choices leads to a more application-optimal technology. We illustrate the design flow by: 1) analyzing the impact of buffer cell design, and 2) by optimizing a 130 nm technology for low operational power.
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
In this paper, the characteristics of the basic current mirror and the continuous-time current-mode current mirror integrator are analyzed. Using the two unlossy loop integrators and the basic current mirrors, the biquad circuit block is implemented. The signal flow graph (SFG) and the improved leap-frog (ILF) structure are simple to implement the six-order band pass filters. Exploring PSPICE9.1 simulation...
In this paper, a new CMOS high performance fully differential second-generation current conveyor (FDCCII) is presented. The proposed FDCCII provides good linearity, high output impedance at terminals Z+ and Z-, and excellent output-input current gain accuracy. Besides the proposed FDCCII circuit operating at a supply voltage of plusmn 1.25 V. The applications of the FDCCII to realize a voltage-mode...
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