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A 0.39 mA 92 dB dynamic range switch-capacitor (SC) third-order ΣΔ modulator for a digital RF hearing aid in 0.35 μm CMOS is presented here. A modified-feedback topology is used here that effectively achieves a high dynamic range and the low power consumption. In the implementation, the bootstrapping-switch and the low-voltage wide-swing OTA are essentially designed for 1.2 V supply voltage with the...
This paper presents a twice the supply voltage bootstrapped switch with the proposed rise time accelerator that has high linearity and fast rising with single phase clock input at low voltage. The proposed rise time accelerator improves rising time and ensures circuit operation at extremely low supply voltage without any complex timing generation circuit. The prototype switch is designed in 65nm CMOS...
This paper introduces new charge and discharge paths to speed up the turn-on and turn-off process of bootstrapped switch. In the mean time, linearity is improved without increasing capacitance or area. The proposed switch is designed in SMIC 65nm CMOS process and the results indicate that total harmonic distortion (THD) of 95dB is acquired when 103MHz input signal is sampled at 1Gsps.
A novel high-speed and low-power negative level shifter suitable for low voltage applications is presented. To reduce the switching delay and leakage current, a novel bootstrapping technique is designed for the level shifter. Furthermore, a pull-down driver is proposed to have high driving capability under different operation modes. The circuit has been designed in 130 nm 1.5 V/5 V triple-well CMOS...
A new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with UMC Mixed-Mode/RF 0.18 ??m 1P6M P-Sub Twin-Well CMOS process by orientating and elaborate designing the switch MOSFETs that have influence on the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feed-through compensation...
A new high-voltage bootstrapped sampling switch with input signal range exceeding 11 times its supply voltage is presented. Proposed switch occupies a silicon area of 250 mum by 160 mum in 0.35 mum twin-well CMOS process with drain extended NMOS (DNMOS) capability. The switch safe input signal range is restricted only by the DNMOS drain terminal breakdown voltage, i.e. 50 V . Implemented switch can...
This paper presents a novel low distortion CMOS bootstrapped switch that adopts a "source track" technique to track the real source terminal of the sampling switch. This technique improves nonlinear distortion due to variation of the gate overdrive and the threshold voltage in conventional switches, acquiring a precise sampling of signal. Based on the SMIC 0.18 mum standard CMOS process,...
This paper presents the design of a highly energy efficient CMOS adiabatic driver (ee-driver). The proposed ee-driver uses an output stage with two bootstrap capacitors driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13 mum CMOS 1.2 V technology, under the large capacitive loading condition, ee-driver performs better...
In this paper, a 10-bit 50-MS/s analog-to-digital converter (ADC) is presented. A power consumption of 10.6 mW is designed by using low power gain-boosted OP-Amp and dynamic comparator. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This circuit is designed in a SMIC 1.2-V 0.13-um CMOS technology. The results show that the proposed Nyquist rate ADC provides a potential...
A 10-b low-voltage CMOS pipelined analog-to-digital converter is described. A low-voltage technique is proposed for pipelined ADC that avoids the use of low-threshold voltage process, on-chip clock voltage doubler, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough...
The nonlinearity of the input sampling switch in a switched-capacitor delta-sigma (DeltaSigma) analog-to-digital converter (ADC) affects the overall performance of the ADC. This can be a problem in modern CMOS process technologies where device threshold voltages do not scale as much as the supply voltage, but is exacerbated in older CMOS/BiCMOS process technologies where very-low threshold voltage...
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