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This paper discussed the applications of electron energy loss spectroscopy (EELS) for element characterization in semiconductor manufacturing. The first experiment compared the ability of element chemical states analysis between EELS and X-ray photoelectron spectroscopy (XPS). Some phase change random access memory (PcRAM) product suffered TiN connection electrode failure. EELS and XPS were used separately...
This paper illustrates physical analysis approach to understand the nature of wafer backside metallization (BSM) discoloration and confirmed the problematic process layer with systematic methodology. A series of analyses are carried out in order to determine the cause of BSM discoloration. Our scanning transmission electron microscopy — energy dispersive X-ray spectroscopy (STEM-EDX) lines scan results...
Ion implantation is the most important silicon doping method in the process of semiconductor manufacturing. The common used analysis methodology such as FIB/SEM/TEM is restricted in analyzing the ion implantation related defects, while the chemical stain technology can provide very essential data in ion implantation process. The etching mechanism of silicon is very complicated with the mixture of...
Reliability of Superjunction (SJ) MOSFET is closely related to its manufacturing process. Experiments are carried out to investigate the electrical characteristics in high temperature of SJ MOSFET produced by deep trench filling technology. Filling holes are confirmed to be responsible for the performance deterioration in high temperature and the mechanism has been analyzed thoroughly.
Large-tilt angle (LTA) implantation has been employed in Si manufacturing processes in many applications, such as lightly-doped drain and Halo Implant. The depth profile of implant ions usually consists of only single peak at incident angle of zero degree with respect to the perpendicular of the silicon surface. However, an abnormal dual-peak profile was observed at LTA (>40 degree) for both boron...
In this paper, we present a study on protective coating techniques for thin film X-TEM sample preparation. The study shows that proper choice of the protective layer before FIB cross section is a crucial step to maintain the film profile and make sure the accuracy of the thickness measurement. Silicon native oxide is used as the target sample. We have investigated PECS metal sputtering followed by...
In this paper, we present one simple die-level backside silicon thinning preparation approach to enable fault localization of vertical trench or highly doped silicon substrate power semiconductor devices. The methodologies are illustrated for understanding and immediate application at any lab environment. Effectiveness of the method is evaluated through qualitative judgement of image resolution clarity...
A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
Zynq System-on-Chip (SoC) integrates both Processor and Programmable Logic architectures, where the whole functionality of a system is placed on a single chip. Due to the advancement of process technology, the complexity of circuit analysis becomes harder and the failure modes are becoming marginal, e.g., leakage in nano-ampere range. SoC devices require very challenging work for failure localization...
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
Thin film deposition process invariably introduces compressive or tensile stress in the films. The stress in a film causes the wafer to warp whose curvature is estimated in a wafer fab using optical reflectance technique. Alternatively, the wafer curvature can also be measured using the high resolution XRD (HRXRD) Si(004) rocking curves. In this paper, the HRXRD technique was employed to evaluate...
The effects of fast neutron radiation up to flux of 1014 cm−2 (1 MeV equivalent flux) upon the turn-on and forward static characteristics of MOS-Controlled Thyristor (MCT) are described in this work, based on physics-based 1-dimension analytical calculation and 2-dimension Silvaco simulation. It is reported for the first time that dependency of on-state specific resistance (Ron) upon neutron flux...
Demand of short failure analysis has been increasing in semiconductor failure analysis. It is known from the previous studies that many short failure analysis methods are suggested. However, it is extremely difficult to identify the short failure location in recent advanced devices due to the fact of optical resolution limit. On the other hand EBAC has been noted as the high resolution method to identify...
This is a case study of an early failure analysis on a chip fabricated on the 40nm technology node. A large leakage current was observed in the high voltage (HV) supply after the chip was stressed as a part of an early failure rate (EFR) test. Electrical failure analysis (EFA) using Backside Emission spectroscopy [1] and Optical Beam Induced Resistance Change (OBIRcH) [2] showed the existence of hotspots,...
Si nanocrystal samples were fabricated by pulsed laser deposition method. Through changing the growth Ar gas pressure, the Si nanocrystal size and density can be controlled. Our works provided a possible way to fabricate Si nanocrystal embedded nonvolatile memory.
The GOX is the most fragile element of a MOS transistor. With the scaling of device, the GOX thickness has been reduced to a few atomic layers, therefore any tiny defects in gate oxide can lead to high leakage current and even gate oxide breakdown. FIB/TEM analysis and chemical wet etching pinhole technology are usually adopted to characterize GOX leakage defect. However, TEM by FIB-cross section...
We have developed a new method to quantitatively evaluate the detectability for voids in bonded wafers by using ultrasonic inspection. The test sample for evaluation consists of bonded two Si wafers and has artificial voids between the wafers. The depths of these artificial voids are 5, 10, 20, and 170 nm. In this study, the evaluation was made by obtaining the images of artificial voids by using...
Although nano-particles have attracted extensive studies in material science and technology for decades, how to measure the particle size efficiently and conveniently still remains to be a problem unsolved. In this paper, Si nano-particles prepared by annealing a very thin amorphous Si layer were inspected by atomic force microscopy (AFM) as well as SEM and TEM e-beam techniques. Results extracted...
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