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A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
Transmission electron microscopy (TEM) is one of the most important characterization techniques in semiconductor failure analysis. However, preparation of a good TEM lamella for analysis has great challenges and requires a well-thought-out sequence of steps. The normal TEM sample preparation procedures, though time consuming, can fulfill majority of the sample requirements, but sometimes there are...
Contamination-free manufacturing environment is essential for semiconductor wafer fabs. Any contaminants from production line such as process tools and chambers need to be closely monitored and well controlled so as to avoid the direct exposure of the production wafers to these contaminants. In this paper, we discussed two typical metal corrosion issues induced by wafer fab environmental contamination,...
As IC manufacturing processes move to smaller feature sizes, fault isolation technique and debug become more and more challenging. In this paper, die level backside fault isolation case studies using emission microscope and scanning laser microscope are presented. They efficiently identified the fault sites in 0.13mum and 90nm products
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