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This paper proposes a fully integrated voltage boost converter with a maximum power point tracking (MPPT) circuit for ultra-low power energy harvesting. The converter is based on a conventional charge pump circuit and can deliver a wide range of load current by using nMOS and pMOS driver circuits for highly efficient switching operation. The MPPT circuit we propose dissipates nano-watt power to extract...
This paper presents a fully autonomous integrated circuit for power conversion from multiple and heterogeneous energy harvesting transducers. Five input channel are dedicated to vibrational harvesting and exploiting multi-frequency operations. Additional four input channels are dedicated to manage DC sources. An independent MPPT is applied on each channel. A relevant feature of the design is the use...
A fully integrated voltage multiplier with low startup voltage (VSTART) and fast startup is developed for the energy harvesting (e.g. thermoelectric energy harvester). The generation of the high frequency clock signal with large amplitude without using off-chip components is a key to achieve the voltage multiplier. The proposed passive clock boost using two on-chip transformers with the winding turns...
This paper presents a novel approach to wide input range capacitive DC-DC converters. The star connected Dickson converter is used, not only for its low bottom plate voltage swing and efficient use of switches, but also for its very regular structure. This regular structure allows it to operate as a folding Dickson converter, implementing several conversion ratios, as well as reusing all of its flying...
This paper presents a fully integrated, reconfigurable switched-capacitor based step-up DC-DC converter in a 28nm FDSOI process. Three reconfigurable step-up conversion ratios (5/2, 2/1, 3/2) have been implemented which can provide a wide range of output voltage from 1.2V to 2.4V with a nominal input voltage of 1V. We propose a topology for the 5/2 mode which improves the efficiency by reducing the...
This paper presents a 5 bit charge-redistribution phase domain ADC (PhADC) implemented in 0.18 µm CMOS technology for low power FSK/PSK demodulation. An IQ-assisted conversion algorithm is proposed to avoid the need for an accurate linear combination of in-phase (I) and quadrature (Q) signals with various scaling factors in a conventional zero-crossing algorithm, thus eliminating the power consumption...
A multi-band autonomous wireless sensor node (AWSN) with temperature monitoring is designed in a standard 0.18 urn CMOS technology. The AWSN comprises a high efficiency energy harvester, a power management module, a temperature-to-time converter (TTC) and a passive 402-MHz MICS band OOK transmitter for backscattering transmission. The AWSN demonstrates a sensitivity of −18.2 dBm at 13.56 MHz. The...
In this work we present Bodysense, a low-power radio with sensor interface for WBAN applications. The SoC comprises a transceiver operating in the frequency range 2.36–2.483GHz and adhering to the IEEE 802.15.6 Narrow Band (NB) and Bluetooth Low-Energy (BLE) standards. The chip was fabricated in a 65nm technology and absorbs 5.5mA/5mA when operating in Rx/Tx mode. The receiver noise figure of 6dB...
An UWB impulse radio transmitter for ultra-low energy neural recording applications is proposed. The transmitter is designed for robust and efficient operation in the 7.25–8.5GHz band, supporting communication ranges in excess to 4m. Powered by a low-voltage 0.5V supply, prototypes in a 130 nm CMOS technology are able to transmit 2.76 pJ/b PPM-modulated pulses to the antenna at a 20Mb/s data rate...
This paper presents an efficient multicarrier 60GHz transmitter for distance measurement (ranging) in an indoor wireless localization system. By exploiting hardware-algorithm co-design, a high precision, high update rate, yet power efficient transmitter architecture is achieved, which comprises subcarrier generation through frequency division, an upconverter, and a power amplifier. An efficient frequency...
This work presents a dual-slope capacitance to digital converter for pressure sensing. The design uses base capacitance subtraction with a configurable capacitor bank and dual precision comparators to improve energy efficiency, consuming 110nW with 9.7b ENOB and 0.85pJ/conv·step FoM. The converter is integrated with a pressure transducer, battery, processor, and radio to form a complete 1.4mm×2.8mm×1...
This paper presents a capacitive sensor interface IC for vortex flow measurements. With this interface, we can measure flows down to half the minumum flow speed of the state of the art, for media temperatures up to 400°C and pressures up to 200 bar in pipes from 15mm up to 300mm diameter, even in the presence of mechanical vibrations, for media ranging from air over oil to mercury. The mechanical...
A THz 31×31 pixel, 100 fps image sensor integrated in a 130 nm CMOS process is presented. Taking advantage of the possibility to modulate the active source that lights the scene, a significant improvement in sensitivity and NEP is achieved by shifting the modulated THz radiation, by means of an antenna/MOSFET, then filtering the signal band using an in-pixel 16-paths passive SC-filter combined with...
This paper introduces a CMOS vision sensor to extract the Gaussian pyramid with an energy cost of 26.5 nJ/px at 2.64 Mpx/s, thus outperforming conventional solutions employing an imager and a separate digital processor. The chip, manufactured in a 0.18 µm CMOS technology, consists of an arrangement of 88 × 60 processing elements (PEs) which captures images of 176 × 120 resolution and performs concurrent...
This paper proposes a high efficiency Class-D amplifier (CDA) with embedded single-inductor bipolar output (SIBO) power module. The characteristics of SIBO converter's bipolar outputs not only suppress equivalent common mode noise but also remove several large external bulky components in conventional boost supply CDA systems. Since bipolar outputs in the SIBO provide independent driving capability,...
To address in the same time high efficiency, high output power and high complexity functions for Signal Processing systems, the partitioning tends to integrate in the same chip some functions of the digital (like DSP) and audio amplifiers (like Class-D) in a deep submicron technology. To fulfill high output power demand without compromising the device's reliability constraints, the amplifier power-stage...
This paper presents a compact, fully-differential instrumentation amplifier with nearly rail-to-rail input common mode range. The amplifier, which is based on an original topology, embodies chopper modulation for offset and flicker noise reduction. The paper describes the experimental results obtained with a prototype designed with the UMC 0.18 µm MM/RF CMOS process. The amplifier draws 42 µA at a...
A dynamic range enhanced readout circuit using current subtraction technique is presented for a capacitive touch screen panels. A low-voltage, analog front-end circuit using a high-voltage input signal is implemented. A high voltage (> 10 V) parallel pulse signal is used as the transmitter signal. The receiver system was designed with low voltage (< 5 V). A current-subtraction circuit (CSC)...
A complementary p-n class-B oscillator with two magnetically coupled second harmonic tail resonators is presented. For the same oscillation amplitude (constrained by reliability considerations) and the same tank, the p-n oscillator achieves 3–4dB better Figure of Merit (FoM) than an n-only reference one. After frequency division by 2, the p-n oscillator has a measured phase noise that ranges from...
This paper presents the co-design of a class-D digitally-controlled oscillator (DCO) and a low-dropout voltage regulator (LDO) generating the supply voltage for the DCO. Despite the high intrinsic supply pushing of the class-D oscillator topology, the LDO noise has only a very marginal impact on the DCO phase noise.
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