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This paper discusses the electrical characteristics of power distribution networks (PDNs) in 3DICs on both system and chip level. In the system-level analysis the global resonance effects in 3D PDNs are highlighted. For chip-level analysis, detailed metal-layer-based power grid model is proposed for the first time for 3D PDNs. With the detailed power grid model, local resonance effects that are unique...
In this paper, we propose a novel design of embedded filter for the noise decoupling between power and ground planes. At its isolation band, this compact filter provides a short path for the return current of the signal. Therefore, it prevents the propagation of the digital switching noise along the power distribution network, and improves the power integrity. This embedded filter provides the noise...
A novel defected ground structure (DGS) with mushroom structures is proposed. This structure is a three-layer structure composed of a patterned metal plane on the top layer and mushroom structures occupying the second and the third layer. It can be applied to a multilayer structure with lower radiation compared with conventional DGS due to its well shielding. Based on slow wave characteristic, this...
The manufacturing of interconnects often leads to conductors with a non-rectangular cross-section. Especially for sharp edges, it is therefore important to study the influence of corner effects on the interconnect circuit characteristics. Firstly, the electromagnetic behavior of a finite conducting 2-D wedge is investigated. Secondly, as an application example, a broadband transmission line model...
In this work, we developed a sophisticated low-cost and wide-band passive equalization method for high-speed differential interconnects. The proposed method was based on a high-pass filter design using parasitics that exist in multi-layer printed circuit board (PCB) interconnects. By employing the parasitics as the filter design components, the proposed passive equalization method offered low-cost...
To reduce simultaneous switching noise (SSN) in a PDN design of TSV-based GPU system, the impedance properties of the hierarchical PDN in the TSV-based GPU system were estimated and analyzed. The system consisted of triple-stacked TSV-based DRAMs on top of the GPU connected by TSVs, a silicon interposer, and a backside re-distribution layer (BS-RDL). A segmentation-based impedance-estimation method...
Lab measurement and simulation results are presented to show how passive capacitive microwave filters along flip-chip package traces can be used to overcome the capacitive discontinuity at the output port of SerDes transceivers to improve link performance. The technique is further developed to demonstrate its ability to shape the near-end eye pattern to improve its height and/or jitter at different...
Increase in processor speeds and recent advancements in processor performance through developments such as multi-core processing and simultaneous multi-threading (SMT) have resulted in a need for faster processor interconnect technology. The Intel® QuickPath Interconnect (QPI) is a high-speed, packetized, point-to-point interconnect used in Intel's next generation of microprocessors. Compared to its...
For high speed signaling, 100Ohm differential impedance has been commonly used for decades. In recent years, 85Ohm differential impedance has been adopted for PCIE Gen2 and Gen3 for better signal integrity performance and routing consideration. However, for storage IOs such as SATA and SAS, buffer, cable, and connector, etc, are 100Ohm design. It is not clear whether we still have better signal integrity...
As DDR4 continues to move from the design phase towards implementation, several challenges have been identified to successfully implement this high performance memory architecture for next generation systems. This paper investigates driver design selection for DDR4 systems. The paper studies the pros and cons of three driver design types namely: standard, pre-emphasis, and de-emphasis on typical net...
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