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Over the past two decades the scaling of IC technologies has reduced device dimensions by more than 20-fold. In the process of this scaling many reliability and parasitic effects have come to dominate the technology design process. Certainly MOS gate reliability and substrate currents (both due to impact ionization and junction leakage) are of major concern. This paper discusses the parasitic effects...
This paper describes a methodology by which accurate MOSFET model parameter sets, covering statistical IC manufacturing fluctuations, can be generated. This procedure employs multivariate statistics to convert correlated device model parameters into a much smaller set of independent manufacturing process-related factors. Worst-case model parameter sets are constructed from the derived factors. Comparisons...
An analysis and modeling of the low frequency noise characteristics of deeply submicronic CMOS devices is conducted. It is shown that the scaling down of the gate area leads to dramatic change of the noise nature and to a substantial increase of the noise level dispersion. A generic modelling of the noise amplitude and spectrum is worked out as a function of geometry and biases, allowing a good representation...
In this paper we review some recent advances made in the field of dopant diffusion modelling in the various materials related with Si CMOS technology. After some information on diffusion in polycrystalline Si, SiO2, and silicides, we develop in more details the case of single crystal Si. A physical model able to handle the interactions between the diffusing dopant and the point defects is briefly...
The main problems which arise in Si CMOS devices while operated at low temperature are investigated. More specifically, the mobility modelling, the influence of impurity freeze-out on LDD resistance, the impact ionization substrate current, the Gate Induced Drain Leakage (GIDL) phenomenon are investigated over a wide range of temperatures (4.2-300 K).
This paper reports on 2D Monte Carlo simulation of two logic inverters. A CML gate is simulated in commutation regime to study the evolution of the propagation delay as a function of the circuit time constants. Furthermore the behaviour of a CMOS inverter under radiation is analyzed.
In this paper we present a combined experimental and theoretical investigation of the capacitance-voltage behaviour of n+ polysilicon/oxide/n+ polysilicon (double polysilicon) capacitors. The theoretical models for the capacitance-voltage behaviour are compared to experimental results, and used to predict how the voltage coefficients of the double polysilicon capacitor are influenced by technological...
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