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In this study, we perform a top gate field effect transistor by using the integration of novel materials such as graphene as active channel and fluorinated graphene as dielectrics on flexible Polyethylene terephthalate (PET) substrate. These device shows high carrier mobility (∼969 cm2/v.s) at a drain bias of +0.5V. It shows good mechanical flexibility and electrical stability after bending measurement...
In this paper, we present a study on protective coating techniques for thin film X-TEM sample preparation. The study shows that proper choice of the protective layer before FIB cross section is a crucial step to maintain the film profile and make sure the accuracy of the thickness measurement. Silicon native oxide is used as the target sample. We have investigated PECS metal sputtering followed by...
In this paper, we present one simple die-level backside silicon thinning preparation approach to enable fault localization of vertical trench or highly doped silicon substrate power semiconductor devices. The methodologies are illustrated for understanding and immediate application at any lab environment. Effectiveness of the method is evaluated through qualitative judgement of image resolution clarity...
A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
Electrochemical migration (ECM) pose a high reliability risk to semiconductor devices. In this study, an ECM caused electrical failure case detail was shared, relevant electrical failure & ECM mechanism was also analyzed. To verify the failure mechanism discussed in this paper, ECM process was simulated on the same chip substrate. Besides, for the first time, the effect of chloride ion concentration...
Forward body bias method for evaluating total ionizing dose (TID) effect in deep sub-micron CMOS integrated circuits is proposed. Without traditionally complicated, time consuming and costly transistor radiation modeling or chip irradiation test, it is demonstrated here that by applying equivalent forward body bias on susceptible NMOS transistors, TID effect evaluation for deep sub-micron CMOS ICs...
In the analysis of plastic packaging SiP product failure, we should not only consider the plastic material and techniques inherent problems, but also the problem that SiP products have a lot of materials, complex structure, and small surface bonding. A type of plastic packaging SiP module function failure after reflow soldering, through appearance inspection, pin electrical characteristic test, X-ray...
Large-tilt angle (LTA) implantation has been employed in Si manufacturing processes in many applications, such as lightly-doped drain and Halo Implant. The depth profile of implant ions usually consists of only single peak at incident angle of zero degree with respect to the perpendicular of the silicon surface. However, an abnormal dual-peak profile was observed at LTA (>40 degree) for both boron...
Butting and inserted pickup layout in MOSFETs leads to substrate resistance shunting effect and serious ESD robustness degradation. This work develops novel layout with external well/ diffusion resistance embedding between the substrate and the grounding terminal in the NMOS transistors. This layout method can greatly enhance ESD performance of the inserted pickup devices. The second breakdown current...
Si nanocrystal samples were fabricated by pulsed laser deposition method. Through changing the growth Ar gas pressure, the Si nanocrystal size and density can be controlled. Our works provided a possible way to fabricate Si nanocrystal embedded nonvolatile memory.
Failure mode is behavior of a component after failure. The confirmation of failure mode is the first and the most important step in a failure analysis. Many symptoms may appear when a component fails, but which are substantial and can be defined as failure modes should be made clear, for failure mode is the direction of a failure analysis and is the key factory of its success, an inaccurate failure...
Large scale and high density packaging of ASICs are usually achieved by FCBGA forms. The structure and materials are more complicated in FCBGA, which would cause reliability concerns in situations where thermo-mechanical stressing is dominant. Accelerated temperature cycling reliability test was performed on 90-nm/8-level copper based FCBGA packaging devices, and open failures dominated by thermo-mechanical...
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