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In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, dry etch process plays an important role in TSV fabrication. TSVs with diameters ranging from one hundred to ten micrometers...
We are developing an active implant for epidural spinal cord stimulation. A thin application specific integrated circuit (ASIC) (∼80 μm) is to be embedded within it. The laser patterned tracks are electrically and mechanically thermosonically bonded on the ASIC pads using gold ball studs, forming micro-rivets through holes in the foil of the tracks, an interconnection method called electrical rivet...
Electrically conductive adhesives are widely used in semiconductor technology. The focus of this work is set on Isotropic Conductive Adhesives (ICA) with a high amount of electrically conductive filler particles. The aim of this work is the material characterization of highly filled epoxy based die attaches materials by dynamic mechanical analysis (DMA) and relaxation experiments in order to derive...
This paper describes the successful process investigations on ultrathin flip-chip bonding for fine-pitch applications on foil, using a novel bonding process involving Isotropic Conductive Adhesives (ICA). A Ag-based B-stage curing ICA was printed using state-of-the-art electroformed stencil on printed Ag circuitry, pre-cured and flip-chip bonded at low bonding force and short duration. The interconnection...
There have been substantial changes in packaging technologies Packages are becoming smaller, thinner and weaker, a variety of chips is packaged together in one package, being stacked upon each other, the bump height for flip chip is becoming smaller and wires are becoming longer and finer.
In system on flex (SOF) packages with high density I/O's, a number of factors induces concentrated stress field around the bonded areas (bumps & traces) during assembly process. For example, the choice of underfill / encapsulant and the associated processes could affect the package integrity. Poor control of the underfill process could potentially result in delamination on various interfaces....
A 3D-integrated test vehicle that emulates noise generation and propagation in a heterogeneous integrated system has been developed. In-stack waveform capturers are embedded on each tier which captured the generation and propagation of noise. A consistent analytical model is created and analysis using that model has allowed us to develop a design strategy for the power delivery network to attenuate...
Modern power electronics is focused on highly efficient, compact and cost-effective converters. In this paper, gallium nitride (GaN) transistors, multicell topology and integrated capacitors are combined to achieve these objectives. The first results of a 48V-to-5V DC/DC 3-level converter using integrated screen printed capacitors are presented. The power board is designed by assembling a ceramic...
In this paper, patterned Cu and Si substrates are interconnected via solder alloys through Al/Ni self-propagating nano-film to obtain hermetical packaging for infrared detector. During the joining process, substrates which are coated with different solder layers (e.g. Sn and AuSn) are bonded under various atmospheres. By optimizing joining parameters, reliable metallurgical joints between Si/Cu and...
This paper brings into light the first prototype miniaturized system-in-package (SiP) microsystems built for wireless body-area-network medical devices which mandate low power consumption and extreme packaging miniaturization. Specifically, this paper focuses on the fabrication of a remote controller for wireless medical devices in the practical shape of an extended “microSD” card where the extended...
Through silicon vias (TSVs) have been used in 3D packaging of microelectronic devices and MEMS devices, where they provide electrical interconnections through the stacked wafers and devices. Currently, chemical vapor deposition (CVD) or electroless deposition are used to partially or fulfill the vias. However, these methods are time consuming. Thus, the potential of inkjet printing to linearly fill...
By using inductive coupling, near-field wireless transceivers can be implemented by digital CMOS circuits and on-chip inductors in standard CMOS process without additional process and no restriction of position. Compared with signal-layer inductor, on-chip multilayer inductors have more complicated and irregular structures and lack of process and design support. However, they are still attractive...
Most of the commonly used lead-free solders have a high melting temperature. However, in many applications a lower processing temperature would be beneficial. Therefore a demand has arisen for reliable lead-free solder with a lower melting temperature. Among the low temperature lead-free solders, Sn-9Zn and Sn-8Zn-3Bi (wt.%) are suitable candidates for many applications, since they offer good mechanical...
The rapid progress in microelectromechanical systems (MEMS) and the evolution from a limited set of well-established applications, examples, in automotive industry, print heads, and digital light projection, to other fields mainly driven by consumer applications (such as image stabilization, smart phones, game consoles, etc.) opens a new market for these devices. It simultaneously creates the need...
Thermo-mechanical stress caused by the mismatch of coefficients of thermal expansion (CTE) and temperature variations remain a major concern for the reliability of semiconductor components. This issue is usually addressed by exposing the component to temperature cycling stress tests for a certain number of cycles, followed by e.g. scanning acoustic microscopy (SAM) to investigate delamination. Discussions...
For WLP (Wafer Level Packaging) thin film polymers play a key role in respect to board level reliability. This paper introduces a reliability indicator giving a tendency of the polymer material to crack initiation around the UBM pad. This indicator derived from Finite Element simulated maximum stress in polymer layer and the material specific tensile strength. Comparing the simulation results with...
Interposer technologies for 2.5D and 3D integration schemes require formation of high density and reliable Through-Package-Vias (TPVs) at high throughput and low cost. Glass is proposed to be an ideal candidate material for interposer applications. Among various methods to form TPVs in glass, a variety of laser processing methods have been proposed as feasible methods. The via hole formation mechanisms...
This paper examines a novel approach to measure residual stresses in an electronic package. The presented method applies a phase-shifted sampling moiré method to X-ray images of the test chip (Si) in the electronic package. In this study, the test chip including an Au bump grid are made by general semiconductor processes for forming Au bumps on Si chip, and X-ray images of the test chip are taken...
Printed electronics is seen as an ultralow cost alternative to current mass produced electronic modules for achieving a simple function or effect. In reality only very basic electronic functions can be realized using purely additive printing and coating techniques. Even for the most simple functional electronic circuit hybrid manufacturing methods need to be employed using elements from standard SMD...
In the Ropas project VTT has developed printed humidity sensors on paper substrate. The goal has been to tailor the humidity sensor performance to be suitable for consumer product use such as on package labels. Printed sensors are thin and flexible, because they are directly printed on paper or plastic substrates. When printed on paper substrate disposability or recyclability is achieved thus making...
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