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A high efficiency class-E outphasing RF power amplifier is presented using a new passive combining circuit. A Power Enhancement Circuit (PEC) and an Efficiency Enhancement Circuit (EEC) are also proposed as part of the combiner that increase output power without violating reliability limits and improve efficiency at power back-off, respectively. The proposed power amplifier is designed in 45nm CMOS...
A single-chip digital polar transmitter integrates an all-digital synthesizer, a PM/AM modulator, and a linearized power amplifier for WCDMA/WLAN. The 1.7∼2.5GHz LO signal is generated from an ADPLL together with a ÷1.5 divider to eliminate DCO pulling. A 2-segment ΣΔ phase modulator enhances the PM bandwidth up to 200MHz, and a digital polar amplifier employs AM-replica linearization to eliminate...
A 60 GHz highly linear Power Amplifier (PA) is implemented in 65-nm Low Power (LP) CMOS technology. The structure consists of four common-source pseudo-differential stages. To improve global performances, a compact transformer-based 8-way power combiner is designed. Three driver stages are neutralized with capacitors to enhance both reverse isolation and power gain. At 60 GHz, the PA delivers a saturated...
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