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A new SRAM cell model, SRAMT, is presented providing a scalable solution to soft error for various energy levels of protection with minimal power consumption and write time penalties. Our model is based on a classic 6 transistor inner core SRAM cell and an outer core consisting of enhanced tri-state inverters. The outer core will absorb a particle strike at a sensitive node of the SRAM cell without...
In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time...
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