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Generation-recombination noise from dual channel MOCVD-grown AlGaN/GaN/AlGaN/GaN HEMTs on sapphire substrate was observed. Local levels with activation energies Ea = 140 meV, Eb= 188 meV and Ec = 201 meV were identified. Devices showed reasonably low values of Hooge parameter (1.06 times 10-4) at room temperature in addition to superior transistor characteristics. The device performance compares favorably...
In this paper, we investigate electron mobility enhancement in uniaxially stressed nMOSFETs with three different channel orientations on a (001) Si substrate. We have experimentally demonstrated that, for stress applied in a [110] direction, electrical results cannot be explained without considering that in-plane masses for the (001) 2-fold valleys (Delta2) are varying with strain. For the first time,...
Shallower junctions must be formed to make transistors work for the 32-nm node. Many kinds of technologies, such as co-implantation, laser spike annealing (LSA), and flash lamp annealing, have been energetically studied to form ultra-shallow junctions. We focused on in-situ doped selective Si epitaxy, with which the short channel effect and the parasitic resistance can be made compatible. Using this...
Performance gap between computation in a chip and communication between chips is widening. "System in a package" (SiP) reduces chip distance significantly, enabling a high-speed and low-power interface. Electrical non-contact interfaces using inductive/capacitive coupling have advantages over mechanical interfaces employing through silicon vias (TSV) and micro bumps. In this paper, a perspective...
Novel test structures were designed for TEM analysis to examine the origin of dielectric breakdown in Cu/low-k interconnect systems, and it was found to be associated with interfacial delamination. Using an electrostatic discharge zapping technique enables the dielectric breakdown monitoring progressively from the interfacial delamination between a SiC capping layer and a SiOC inter-dielectric layer...
This paper deals with the investigation of mechanisms leading to a degradation of the electrical properties of titanium nitride - aluminum oxide - titanium nitride capacitors at high temperatures. Several degradation mechanisms could be identified by thorough electrical and physical characterization. The findings will serve as a future guide to build thermally stable MIM capacitors
The reliability of recess-channel gate (RG) cell transistor under positive bias Fowler-Nordheim (F-N) gate stress and gate-induced drain leakage (GIDL) stress was investigated. RG cell transistor was found to be more degraded by the F-N gate stress than the GIDL stress due to the gate oxide thickness profile of the RG structure. The oxide thickness along the sidewall plane is a critical factor determining...
Continued shrinkage of floating gate devices requires scaling of the tunnel and/or interpoly dielectrics. This leads to increasing leakage currents that jeopardize the nonvolatile memory retention requirements. High-k materials are natural candidates to enable further scaling of the tunnel/interpoly dielectrics. In this paper, we present an analysis of the defects in Al2O3-based stacks. It is found...
A technique has been developed to fabricate transistors using a continuously scaled 0-2.5 nm SiO2 interface layer between a silicon substrate and high-κ dielectric on a single wafer. Transistor results are promising with good mobility values and drive current. The slant etching process has no detrimental effect on the electrical characteristics of the Si/SiO2 interface. This technique provides a powerful...
In this paper, we analyze the experimental SILC statistical data at low stress reported in (Driussi et al., 2005) . To this purpose we developed an analytical physical model to study the statistical distribution of the TAT current due to single and multiple traps in the gate oxide of a floating gate memory cell. We modeled also the generation dynamics of conductive percolation paths due to more traps...
An extensive gate-length (LG) dependent electrical characterization of silicon nanowire (NW) field effect transistors (FET) is presented here. Catalytically-grown and nominally undoped Si-NWs were integrated as the active region of FETs, upon which fully silicided Schottky source and drain contacts were fabricated. The length of the active region was shortened by a desired value, through the lateral...
This work reports on the fabrication, characterization and modeling of single electron transistor behavior in gate-all-around silicon nanoscale MOS devices. Polysilicon-gated nanowire transistors with triangular cross-sections, ranging from 20 to 250nm are fabricated by an original isotropic etching technique resulting in localized-SOI on bulk-Si wafers. Low temperature (T<20K) characteristics...
A kerf and tester compatible test structure is presented which allows fast and reliable evaluation of resistance and capacitance values of DRAM memory cells. The circuit is realized in a 70nm DRAM process, consumes an area of 795mum times 76mum, and requires six interconnect pads. Using standard electrical measurement equipment, the characterization method reveals resistance and capacitance based...
A simple technique for monitoring floating gate (FG) charge gain/loss with elementary charge accuracy is proposed. The technique does not require nanoscale FG or low temperature and can be applied to virtually any submicron FG memory cell. The potential applications include precise capacitance measurements, as well as analysis of program, erase, disturb and data retention characteristics of FG memory...
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