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Despite strong scaling limitations for both NOR and NAND flash memories, solutions to continue the Moore's law are also emerging. For NOR flash memory, 2-bit/cell NROM, BE-SONOS and phase-change chalcogenide memory show promise to scale below 35nm node. For NAND flash memory, new nitride storage devices such as TANOS and BE-SONOS are candidates for < 30 nm devices
Negative bias temperature instability (NBTI) of p-MOSFETs gets recovered immediately when the stress is removed, and hence the electrical measurement will tend to underestimate the NBTI degradation due to its unavoidable measurement time. This measurement-induced additional NBTI recovery must also be taken into account, especially during the NBTI recovery process, because it directly affects the time...
In this paper, we discuss the physical principles of set of new measurement techniques to explore the reliability limits of (time dependent) dielectric breakdown (TDDB) and negative bias temperature instability (NBTI), two major reliability concerns of high performance logic/memory transistors. Our analysis of the techniques provides a sound theoretical foundation of the measurement algorithms. This...
This paper report on the reliability properties of microwave-plasma deposited ultrathin high-k gate dielectric (ZrO2 ) films on strained-Si/SiGe layers. Stress induced leakage current; trap centroid and charge trapping behavior under constant current and voltage stressing in both polarities have been studied
It is known that Ge condensation is achieved by thermal oxidation of the SiGe layer whereby Si oxidizes faster as compared to Ge, and the Ge atoms are rejected from the oxide into the SiGe layer below. As the Ge diffusion and accumulation varies with gas flow and temperature, detailed investigations are carried out and process conditions are optimized in this work. The accumulation and diffusion mechanism...
Nanostructure characterization of carbon nanofibers (CNFs) for on-chip interconnect applications is presented. We propose a novel technique for characterizing interfacial nanostructures of vertically aligned CNFs, optimally suited for cross-sectional imaging with scanning transmission electron microscopy (STEM). Using this technique, vertically aligned CNFs are selectively grown by plasma-enhanced...
The evolution of laser sources has led to the advent of new laser-based techniques for failure analysis. The pulsed OBIC (optical beam induced current) technique is one of them, which is based on the photoelectric laser stimulation of the device under test (DUT) at a micrometric scale. The suitability of this technique to localize failure sites resulting from electrostatic discharges (ESD) has previously...
A proposed method for failure analysis and debugging of electrostatic discharge protection in VLSI circuits is presented, based on low-energy non-destructive emulation of real ESD stress. It allows on-die current and voltage measurements during stress, providing a direct and clear conclusion about the proper functioning of the protection method, or a reason for failure
Recent fundamental studies have given rise to the emergence of new applications for carbon-based nanostructures in electrical and biological systems. In this paper, our recent work investigating the utility of carbon nanotube (CNT) and carbon nanofiber (CNF) devices in electrical and biological interconnect systems is reviewed. Electrical and structural characterizations of carbon nanostructure arrays...
Electrical and SEM analysis of gate-silicided (GS) and gate-non-silicided (GNS) ESD NMOSFETs in a 65nm bulk CMOS technology show that the failure mechanism switches away from classical drain-to-source filamentation when the silicidation between the silicide-blocked drain/source and the polysilicon gate is avoided. For 2.5V thick oxide devices, drain-to-substrate junction shorting was observed, whereas,...
In this work, we investigate the effects of oxidation temperature and annealing on Ge movement, and amorphization as an undesirable consequence of inappropriate lowering of temperature during Ge condensation. Possible mechanisms, solutions and implications are presented and it is shown that SiGe with up to 60% Ge can be obtained with oxidation and annealing at a high temperature of 1050degC
In this paper, we demonstrate for the first time via technology computer aided design (TCAD), the enhancement in both the ac and dc performances for process-induced strained-Si MOSFETs over bulk-Si and a comparison of process-induced strained and substrate-induced strained-Si MOSFETs. In addition, we present the hot-electron degradation characteristics for strained-Si n-MOSFETs fabricated in both...
This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (Olap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V g lead...
The seemingly relentless progress of Moore's law recently transformed the basic nature of semiconductor test. Today the focus on the high-end devices is evolving from precise measurement to data management. A transaction-based ATE architecture is therefore described
This paper reports burn-in test results of Cu/low-K (BD) interconnects on flexible organic substrate (FR-4,0.1mm) and Si substrate. The electrical yields of via chains (via number: 11,182, via size: 0.26 to 0.5 mum) onto flexible organic substrate remain more than 50% and surviving via chains exhibit average resistance shift of 7.3% which is comparable to Si substrate (6.8%) after 524hrs (388hrs/75degC...
In summary, the implementation of a Co(W,P) cap only on the Cu lines is able to improve the dielectric breakdown performance in Cu/low-k interconnects. This is due to the elimination of the weak interface between the cap and the low-k dielectric. However, the thickness of the Co(W,P) cap needs to be optimized in order to fully benefit from the breakdown improvement while maintaining its efficiency...
As semiconductor process technology rapidly develops into deep-sub-micron or nanometer regime, the feature size of semiconductor devices continues to shrink down. As a result, the defect being able to cause a device malfunction is also becoming smaller and smaller, and even certain defect is invisible with high-resolution SEM or TEM. It makes conventional physical failure analysis (PFA) face a great...
In power electronics, often control and power part are at different electric potentials. Thus, electrically isolated coupling of them is performed by optocoupling devices. Also, isolating DC/DC converters are in use. While such systems are dedicated for high reliability application, weak points within these small components generate problems to the system reliability. The paper outlines most common...
This paper presents a successful methodology for TEM sample preparation on indium pre-form thermal interface material (TIM), which is currently used in high-performance microprocessor product. Experimental results show that FIB related artifacts are greatly reduced, thus enables phase morphology study of inter-metallic compound (IMC) layers between TIM and IC chip
Increased packing density and reduced device size leads to increase in the back-end related delays. This happens as a result of increase in the metal resistance due to decreased line-width and increased capacitance due to a higher density of the interconnects. To minimize the impact of interconnect related delays (RC delay) the semiconductor industry had to, as a first order change, look for metal...
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