The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
This paper focuses on the future semiconductor manufacturing challenges. Some background information regarding the possible limits of scaling and the problems appeared in the sub-100 nm devices will be discussed, respectively, in section 2 and 3. The impacts of the future semiconductor manufacturing will be discussed in section 4. We shall also look forward to the possible geographical redistribution...
Despite strong scaling limitations for both NOR and NAND flash memories, solutions to continue the Moore's law are also emerging. For NOR flash memory, 2-bit/cell NROM, BE-SONOS and phase-change chalcogenide memory show promise to scale below 35nm node. For NAND flash memory, new nitride storage devices such as TANOS and BE-SONOS are candidates for < 30 nm devices
In this paper, we discuss the physical principles of set of new measurement techniques to explore the reliability limits of (time dependent) dielectric breakdown (TDDB) and negative bias temperature instability (NBTI), two major reliability concerns of high performance logic/memory transistors. Our analysis of the techniques provides a sound theoretical foundation of the measurement algorithms. This...
Negative bias temperature instability (NBTI) of p-MOSFETs gets recovered immediately when the stress is removed, and hence the electrical measurement will tend to underestimate the NBTI degradation due to its unavoidable measurement time. This measurement-induced additional NBTI recovery must also be taken into account, especially during the NBTI recovery process, because it directly affects the time...
In this paper, a new twin gated-diode (T-GD) method has been greatly improved for the oxide interface characterization of MOS devices with gate oxide as thin as 1 nm (EOT). With the scaling of gate oxide thickness into 1 nm regime, reported GD measurement can not give correct measurement due to gate tunneling leakage current. Here, we provide a simple method to remove this limitation. This method...
Companies estimate the NBTI lifetime of SRAM memories usually by extrapolation of the DC degradation. This method underestimates the lifetime of the memory cell since the bit change in the cell over time is neglected. In this work we have analyzed the impact of storing random bit values in a 6T-SRAM memory cell by using probabilities of storing a one bit between the boundaries of 100% (fully unsymmetric...
The effect of gate-oxide reliability in MOSFET on common-source amplifiers is investigated with the non-stacked and stacked structures in a 130-nm low-voltage CMOS process. The supply voltage of 2.5 V is applied on the amplifiers to accelerate and observe the impact of gate-oxide reliability on circuit performances including small-signal gain, unity-gain frequency, and output DC voltage level under...
This work illustrates succinctly the ability of the SCEM to provide valuable information for metrological studies of thick non-optically transparent semiconductor devices. The utility of SCEM to failure analysis comes from its ability to provide relatively high-resolution images from extremely thick specimens. In this way, the instrument can bridge the gap between optical SCOM useful for observing...
Using a circular beam separator to deflect the primary beam of an SEM through 90deg, an aberration limited final probe size of 7-8 nm has been achieved in experiments. This limit was shown to be due to magnetic leakage fields from the post-deflector lens and not due to aberrations of the beam separator. In fact, it is concluded that the beam separator aberrations are within 2 nm over a 1 mum by 1...
The combined use of scanning probe microscope based techniques, namely conductive atomic force microscopy (C-AFM) and tunneling atomic force microscopy (TUNA), and nanoprobing technique is presented. In 90 nm process and below, C-AFM identifies leakage by current mapping, while TUNA measures the current-voltage (I-V) curves of different contacts to study the integrity of individual contacts. Nanoprobing...
The importance of understanding asymmetrical behaviour in SRAM has increased as the technology node shrinks below 100 nm. Single bit failure can possibly be caused by the malfunction of any of the six transistors in a standard SRAM cell. In order to understand the asymmetrical behaviour in advanced nano SRAM devices, nanoprobing is introduced to perform transistor level fault isolation prior to attempting...
Surface charging is encountered in the study Auger electron spectroscopy of non-conducting surfaces. In this paper, two case studies of (i) Au-pad of packaged die unit and (ii) floating Al-pads of patterned wafer were presented. Surface charging was noticed in both the samples and it was not possible to eliminate the effect with convention charge reduction methods. Two FIB-based methods of charge...
The paper could limit itself to repeat the complaint that originated the first "Rules of the Rue Morgue", maybe updating the scenario of the many end users currently exposed to the risk of failed failure analyses. Nevertheless, some constructive proposals will be also pointed out, as those exposed by a recent paper (Cassanelli et al., 2005) that, dealing with the challenges in system reliability...
In this paper, experimental features of a non-classical hot-electron gate current Ige obtained under Vb = 0, similar to those reported earlier under reverse Vb are presented. To the best of our knowledge, this is the first direct observation of this non-classical Ige component in deep submicrometer N-channel MOSFET under conventional CHE biasing, i.e. when Vg ap Vd and Vb = 0. Based on the results,...
This paper presents reliability investigations in NLDEMOS transistor in 0.13μm SOI CMOS technology. Reliability tests under hot carrier injections (HCI) for different gate-lengths show two different degradation mechanisms. The modification of current path with short overlap (Olap) due to oblique equi-potential lines and the increase in the vertical electrical field under the gate edge at low V g lead...
Two phases during the P/E cycling of 0.18mum SONOS are observed using a combined charge pumping method to extract the trapped charge distribution: holes accumulation at the initial term, and electrons accumulation after long term cycling. Better endurance characteristic is obtained through optimization to P/E condition and process technology
In this study, we propose a LSC technique that using SiN capping layer deposition with high mechanical stress on single poly-Si gate. In addition, nMOSFETs with thicker poly-Si gate (220 nm) can also increase tensile strain in the channel region compared to that of the thinner (150nm) poly-Si gate structure. Furthermore, size dependence of nMOSFETs with SiN capping layer is also studied and compared...
Semiconductor optical amplifiers (SOAs) appear as key components for many applications for future optical networks and telecommunication systems due to various technological schemes that can be selected according to the targeted functions and performances (Eliseev, 1995). New qualification methodologies are now proposed to face the optoelectronic industry modifications and provide end-users with relevant...
In this paper, we demonstrate a practical alternative to the conventional SIL, which overcomes the above limitations. We show that it is possible to fabricate a lens directly on the back side of the silicon of the device under test. This lens works on principles of diffractive optics and is around 250 nm thick. The lens may be fabricated in about 1 hour, using a combination of FIB ion implantation...
During the development and qualification of a 300mm low-k/Cu back end of line (BEOL) technology, the long-term reliability of such interconnects including low-k time-dependent dielectric breakdown (TDDB), Cu electromigration (EM), Cu stress migration (SM), and Cu/low-k thermal behavior are rapidly becoming one of the most critical challenges. In this paper, a comprehensive reliability evaluation for...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.