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We report record breaking values for PMOS source drain (S/D) contact resistivity, ρc < 10−9Ω·cm2. These were obtained by shallow Ga ion implantation on Si0.4Ge0.6 in combination with subsequent pulsed nanosecond laser anneal (NLA). Cross section transmission electron microscopy (XTEM) shows the pc reduction mechanism is based on Ga and Ge segregation towards the surface.
Following the previous study on Si:P [1], we also achieve ultralow contact resistivities (ρc) of ∼2×10−9 Ω·cm2 on Si0.3Ge0.7:B using the same Ti based pre-contact amorphization (PCAI) plus post-metal anneal (PMA) technique. Similar as on Si:P, low-energy PCAI provides the lowest ρc on SiGe:B. By increasing the B concentration, the PMA temperature required on SiGe:B also matches with that on Si:P....
Scaling of semiconductor devices over past decades has been made possible by continuous innovations in materials engineering as well as device integration and geometries. Thermal processing has been an enabler for manufacturing advanced devices, both as a unit process and in concert with other key technologies like ion implantation, epitaxy, and film deposition. This paper reviews the evolution of...
Applied materials rapid thermal processing (RTP) systems are unique in providing high resolution process data particularly wafer rotation angle and wafer rotation speed as a function of time. This work explores how this information can be used to predict on-wafer process results using an advanced analysis package known as WISR (wafer interdiction and scrap reduction). WISR is an advanced process control...
The Applied Materials RTP systems are unique in providing high resolution process data particularly lamp power and temperature as a function of radial position and time. This work explores how these data can be exploited to predict on-wafer process results using an SPC analysis package named WISR. WISR is an advanced process control platform for collection, storage, visualization, and analysis of...
The impact of the silicon surface contaminants iron, copper and calcium on gate oxide integrity was investigated quantitatively by evaluating MOS test capacitors built on intentionally contaminated wafers. All three elements influenced dielectric breakdown field strength and charge to breakdown values if the surface contamination level was raised beyond 10 9 to 10 10 atoms/cm...
The oxidation rate of single crystalline silicon depends on the preoxidation cleaning procedure. Various cleaning procedures were compared using aqueous solutions of NH4OH-H2O2, HCl-H2O2 and H2SO4??H2O2?? A dip in 10% HF was used either at the beginning or at the end of the cleaning procedure. Thermal oxidation was carried out at 885??C, 985??C and 1085??C in a conventional diffusion furnace. The...
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