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Systematic experiments demonstrate the presence of the kink effect even in FDSOI MOSFETs. The back-gate bias controls the kink effect via the formation of a back accumulation channel. The kink is more or less pronounced according to the film thickness and channel length. However, in ultrathin (<10 nm) and/or very short transistors (L < 50 nm), the kink is totally absent as a consequence of super-coupling...
Metal gate/high-k LSTP CMOSFETs for sub-32nm technology was demonstrated using a novel-damage free neutral beam-assisted atomic etching process. Due to its neutralized atomic flux and chemical reaction, it had a high etch selectivity, oxygen concentration control and improved device performance/reliability. NBALE is a key process for reducing GIDL and Ioff control which is a key factor for LSTP.
The dissociation rate of the Si-H bond at Si/SiO2 interface under NBTI stress condition considering the quantum effect on the hole density in the inversion layer of the MOSFET is calculated. By adopting the DG method with the penetration boundary condition and the WKB approximation, the penetrated hole density profile in the gate oxide and the tendency of the amount of hole at Si-H bond according...
A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values...
Record breaking RF performance was recently achieved on a 65nm CMOS technology (29nm Lgate, 210nm pitch) employing uni-axial strained silicon transistors. These highest-reported cutoff frequencies for NMOS transistors achieve fT/fMAX values of 360 GHz/420 GHz. PMOS transistors also demonstrate superior performance with fT/fMAX values of 238 GHz/295 GHz. Varactor performance on this substrate technology...
Integration of stress proximity technique (SPT) and dual stress liners (DSL) has been demonstrated for the first time. The proximity of stress liner is enhanced by spacer removal after salicidation and before the DSL process. It maximizes the strain transfer from nitride liner to the channel. PFET drive current improvements of 20% for isolated and 28% for nested poly gate pitch devices have been achieved...
A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression...
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