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Continuous scaling down NAND FLASH toward below 2Xnm node generation will result in serious Floating Gate (FG) poly depletion due to dopant loss and significantly degrade the cell reliability performance. FG implantation (IMP) before inter-poly-dielectric (IPD) deposition was proposed in this study, but it suffered FG damage and resulted in control gate (CG) void issue. We have successfully minimized...
The oxide loss behavior of buffered hydrofluoric (BHF) acid etch solution with elapsed time was investigated with and without advanced process control system (APC). The oxide loss amount increases with increasing the elapsed time in etching solution of BHF. The variation of BHF solution is considerable improved by at least to zero at run to run with APC. The result indicates this system is a promising...
With the rapid increase of automobile holdings in the domestic, how to effectively manage vehicles in regional range and improve the effective utilization of limited resources are problems that cannot be ignored by the team managers. In order to solve the above problem, this thesis takes “Peace travel” ubiquitous network demonstration system as the background, based on the technology of Flex, proposes...
In this brief, high-κ HfZrO (via atomic layer deposition) fabricated by a novel multideposition multiroom-temperature annealing (MDMA) technique in ultraviolet-ozone (UVO) ambient is systematically investigated by both electrical and physical characterization and is integrated with a TiN metal gate in a gate-last process. Compared with the conventional rapid-thermal-annealed sample, it is found that...
An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device,...
For Solid-State Drive (SSD) applications cycling endurance of NAND flash is a critical challenge. In this work the endurance reliability of BE-SONOS NAND is thoroughly examined. Using dual CV/IV tests the impact of interface state (Dit) generation/annealing and real charge trapping (Q) on the endurance degradation has been clearly identified. For BE-SONOS with pure thermal oxide O1, the endurance...
Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits...
The present study investigates the charge trapping characteristics of Si-rich nitride thin films in detail by using the gate-sensing and channel-sensing (GSCS) method. Analytical results indicate that thicker (>7 nm) nitride thin films are fully-capturing; the trapped electrons are distributed in the center of the nitride, and the charge centroid is independent of the N/Si ratio. However, thinner...
In NAND flash, devices are normally erased to negative Vt and then programmed to positive Vt. In this work we introduce a novel depletion-mode (normally on) buried-channel, junction-free n-channel NAND flash device. The buried-channel NAND flash shifts the P/E Vt ranges below those for the conventional surface-channel device, and is more suitable for the NAND Flash memory design. Due to the lower...
A bandgap engineered SONOS with greatly improved reliability properties is proposed. This concept is demonstrated by a multilayer structure of O1/N1/O2/N2/O3, where the ultra-thin "O1/N1/O2" serves as a non-trapping tunneling dielectric, N2 the high-trapping-rate charge storage layer, and O3 the blocking oxide. The ultra-thin "O1/N1/O2" provides a "modulated tunneling barrier"...
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