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The effect of flatband-voltage reduction [roll-off (R-O)], which limits fabrication options for obtaining the needed band-edge threshold voltage values in transistors with highly scaled metal/high- k dielectric gate stacks, is discussed. The proposed mechanism causing this R-O phenomenon is suggested to be associated with the generation of positively charged oxygen vacancies in the interfacial SiO...
This paper describes a design and implementation of low-power and high-speed security hardware cores for the advanced encryption standard (AES) and the secure hash algorithm (SHA1). We propose three register transfer level (RTL) circuit techniques, namely, application specific register reduction (ASRR), locally explicit clock enabling (LECE), and bus specific clock (BSC). LECE and BSC can be used...
Effect of the flat band voltage reduction (roll-off) in highly scaled high-k/metal gate stacks is discussed. The proposed mechanism explains the roll-off phenomenon as caused by the metal electrode/high-k dielectric-induced generation of positively charged oxygen vacancies in the interfacial SiO2 layer in the high-k dielectric stack. The model is consistent with the observed roll-off dependency on...
In this paper an optimum device design of SONOS flash memory devices with spacer-type charge trapping layer formed on the side surface of recessed channel region is discussed. The device can be applied to high- density and high-performance 50 nm NOR-type flash memory cell. The nitride length of 60 nm from the top of the body is reasonable 2-bit/cell operation at a S/D junction depth of 30 nm.
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