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We present the design and analysis of a power-efficient cascode-compensated amplifier. The proposed analysis is based on an intuitive approach that simplifies the design of sucn structures. Based on this analysis, an amplifier in UMC 0.18 µm technology is designed. Cascode compensation, along with other power saving techniques, results in a power efficient amplifier with a relatively high figure of...
The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in the proposed approach all filter sections operate at the sampling frequency of the modulator. The low power dissipation is in this case achieved...
The paper presents a new CMOS implementation of the initialization mechanism for Kohonen self-organizing neural networks. A proper selection of initial values of the weights of the neurons exhibits a significant impact on the quality of the learning process. A straightforward realization of the initialization block in software is simple, but in hardware it requires providing the programming signal...
In this paper, the design of a low-noise amplifier (LNA) for a 32×32 pixel microelectrode array (MEA) is presented. Its gain and noise amount to 50 dB and 10μVrms, respectively, at a bandwidth of 66kHz. The LNA consumes less than 85μW. The integrated offset compensation circuit makes the system less sensitive to mismatch and variations in the culture medium biasing voltage. A sample& hold (S&H)...
A prototype of a high-density multielectrode array for in vitro recording of electrogenic cell networks has been developed. On a surface of 1.92×1.92mm2, it includes 32×32 pixels with a dimension of 60×60μm2. For local amplification of the sensed extracellular signals, two fully differential low-noise amplifiers with offset reduction circuit have been designed. According to simulations, they feature...
This paper describes some of the design experiences achieved during the design, simulation and characterization of a Complementary Metal-Oxide Semiconductor (CMOS) LNA which has been designed for 24GHz and fabricated in a standard 0.180 μm technology. More specifically, some technological limitations of the CMOS process for mm-wave applications are considered, before showing the outcomes of the schematic...
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