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Silicon nanowire FET (SiNWFET) with dynamic polarity control has been experimentally demonstrated and has shown large potential in circuit applications. To fully explore its circuit-level opportunities, a physics-based compact model of the polarity-controllable SiNWFET is required. Therefore, in this paper, we extend the solution for conventional SiNWFETs to polarity-controllable SiNWFETs. By solving...
This letter demonstrates the first fabricated four-transistor logic gates using polarity-configurable, gate-all-around silicon nanowire transistors. This technology enhances conventional CMOS functionality by adding the degree of freedom of dynamic polarity control n- or p-type. In addition, devices are fabricated with low, uniform doping profiles, reducing constraints at scaled technology nodes....
We extend ambipolar silicon nanowire transistors by using three independent gates and show an efficient approach to implement dual-threshold-voltage configurable circuits. Polarity and threshold voltage of uncommitted devices are determined by applying different bias patterns to the three gates. Uncommitted logic gates can thus be configured to implement different logic functions for dual-threshold-voltage...
In this paper a potential based model for monocrystalline silicon thin film transistor (TFT) systems on glass (SOG) substrate from the accumulation to the strong-inversion region is developed. By solving the complete dimensional (1D) Poisson's equation, the potential distribution in the channel is obtained. The analytic drain current is expressed accurately base on the potential solution. Compared...
A generic DG MOSFET analytic model with vertical electric field induced mobility degradation effects is proposed and verified in this paper. It is shown that the proposed model is valid for different operation modes including symmetric DG (sDG), asymmetric DG (aDG) and independent DG (iDG). Extensive two-dimensional (2-D) device simulation is performed to verify the proposed model.
ULTRA-SOI is a new generation of the channel-potential-based non-charge-sheet model for the dynamic depletion (DD) Silicon-On-Insulator (SOI) MOSFET, developed by TSRC group in EECS department of Peking University with many year efforts. The model is formulated with a fully physical derivation from the Poisson's equation to solve the potential along the vertical direction of the silicon film. The...
In this paper an analytic model for Ge/Si core/shell nanowire MOSFETs (NWFETs) is developed. First, the electrostatic potential and charge model are derived out from classical device physics. Then the drift-diffusion drain current model is obtained and verified by comparisons with the numerical simulation. The ballistic current model is obtained with the approximately described quantum-mechanical...
An analytic surface potential based non-charge-sheet model for poly-silicon thin film transistors (poly-Si TFTs) is proposed in this paper with consideration of the substrate and film thickness effects. The 1-D Poissonpsilas equation with dopant, mobile, and the trap charge terms is first solved to obtain accurate yet continuous channel potentials physically. An analytic non-charge-sheet drain current...
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