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This paper presents an analysis on the high temperature operation of Silicon-on-Insulator (SOI) nMOSFETs in Asymmetric Self-Cascode (A-SC) configuration. For this analysis, experimental results in the range of 300K to 500K of A-SC structures with different channel lengths for both the drain side transistor (MD) and source side transistor (MS) are used. The effect of varying channel length under high...
This paper presents an analysis on the linearity of Asymmetric Self-Cascode (A-SC) of FD SOI nMOSGET transistors at cryogenic temperatures. This is achieved by evaluating experimental results of associations of transistors with various combinations of channel doping, obtained at temperatures ranging between liquid helium temperature (LHT, 4K) and room temperature (300K). It has been observed that...
This paper presents an experimental analysis of channel length influence on the analog characteristics of asymmetric self-cascode association of SOI transistors. It is shown that the increase of the drain current and transconductance is more pronounced with the reduction of the length of the transistor close to the source (L1), and, differently from the symmetric self-cascode, suffers little influence...
This work presents an analysis of the analog performance of asymmetric threshold voltage self-cascode fully depleted (FD) p-type SOI transistors. The experimental results showed that this structure is able to improve the devices transconductance and output conductance, resulting in increased intrinsic voltage gain and breakdown voltage in comparison to single transistors and the conventional symmetric...
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